]> git.sur5r.net Git - u-boot/blobdiff - board/atum8548/atum8548.c
p1022ds: use weak CFI flash accessors when DIU is enabled
[u-boot] / board / atum8548 / atum8548.c
index da6cf47433d07c1e67be562828228f889fc3bd19..671f9e985364ef2084bd465d1998fef569755987 100644 (file)
@@ -47,7 +47,7 @@ int board_early_init_f (void)
 int checkboard (void)
 {
        volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-       volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+       volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
        volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
 
        if ((uint)&gur->porpllsr != 0xe00e0000) {
@@ -219,7 +219,7 @@ void pci_init_board(void)
                pcie1_hose.region_count = 1;
 #endif
                printf ("    PCIE1 connected to Slot as %s (base addr %lx)\n",
-                               pcie_ep ? "End Point" : "Root Complex",
+                               pcie_ep ? "Endpoint" : "Root Complex",
                                pci_info[num].regs);
 
                first_free_busno = fsl_pci_init_port(&pci_info[num++],
@@ -292,14 +292,6 @@ void ft_board_setup(void *blob, bd_t *bd)
 {
        ft_cpu_setup(blob, bd);
 
-#ifdef CONFIG_PCI1
-       ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
-#endif
-#ifdef CONFIG_PCI2
-       ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
-#endif
-#ifdef CONFIG_PCIE1
-       ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
-#endif
+       FT_FSL_PCI_SETUP;
 }
 #endif