ARM: atmel: sama5d4_xplained: enable spl support

[u-boot] / board / bf537-stamp / post-memory.c

diff --git a/board/bf537-stamp/post-memory.c b/board/bf537-stamp/post-memory.c
index 9626f4cd7af0bda5832a83159e0de5c4ea52cb75..2dea92fbe9b80149a387df55a1e3e08958a00147 100644 (file)
--- a/board/bf537-stamp/post-memory.c
+++ b/board/bf537-stamp/post-memory.c
@@ -1,8 +1,6 @@
 #include <common.h>
 #include <asm/io.h>
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 #include <watchdog.h>
 
@@ -15,7 +13,6 @@
 #define SCLK_NUM       3
 
 void post_out_buff(char *buff);
-int post_key_pressed(void);
 void post_init_pll(int mult, int div);
 int post_init_sdram(int sclk);
 void post_init_uart(int sclk);
@@ -54,7 +51,7 @@ int memory_post_test(int flags)
                sclk_temp -= CONFIG_SCLK_DIV;
        sclk = sclk * 1000000;
        post_init_uart(sclk);
-       if (post_key_pressed() == 0)
+       if (post_hotkeys_pressed() == 0)
                return 0;
 
        for (m = 0; m < CCLK_NUM; m++) {
@@ -99,19 +96,19 @@ void post_init_uart(int sclk)
        for (divisor = 0; sclk > 0; divisor++)
                sclk -= 57600 * 16;
 
-       *pPORTF_FER = 0x000F;
-       *pPORTH_FER = 0xFFFF;
+       bfin_write_PORTF_FER(0x000F);
+       bfin_write_PORTH_FER(0xFFFF);
 
-       *pUART_GCTL = 0x00;
-       *pUART_LCR = 0x83;
+       bfin_write_UART_GCTL(0x00);
+       bfin_write_UART_LCR(0x83);
        SSYNC();
-       *pUART_DLL = (divisor & 0xFF);
+       bfin_write_UART_DLL(divisor & 0xFF);
        SSYNC();
-       *pUART_DLH = ((divisor >> 8) & 0xFF);
+       bfin_write_UART_DLH((divisor >> 8) & 0xFF);
        SSYNC();
-       *pUART_LCR = 0x03;
+       bfin_write_UART_LCR(0x03);
        SSYNC();
-       *pUART_GCTL = 0x01;
+       bfin_write_UART_GCTL(0x01);
        SSYNC();
 }
 
@@ -123,8 +120,8 @@ void post_out_buff(char *buff)
                ;
        i = 0;
        while ((buff[i] != '\0') && (i != 100)) {
-               while (!(*pUART_LSR & 0x20)) ;
-               *pUART_THR = buff[i];
+               while (!(bfin_read_pUART_LSR() & 0x20)) ;
+               bfin_write_UART_THR(buff[i]);
                SSYNC();
                i++;
        }
@@ -132,76 +129,16 @@ void post_out_buff(char *buff)
                ;
 }
 
-/* Using sw10-PF5 as the hotkey */
-#define KEY_LOOP 0x80000
-#define KEY_DELAY 0x80
-int post_key_pressed(void)
-{
-       int i, n;
-       unsigned short value;
-
-       *pPORTF_FER &= ~PF5;
-       *pPORTFIO_DIR &= ~PF5;
-       *pPORTFIO_INEN |= PF5;
-       SSYNC();
-
-       post_out_buff("########Press SW10 to enter Memory POST########: 3\0");
-       for (i = 0; i < KEY_LOOP; i++) {
-               value = *pPORTFIO & PF5;
-               if (*pUART0_RBR == 0x0D) {
-                       value = 0;
-                       goto key_pressed;
-               }
-               if (value != 0)
-                       goto key_pressed;
-               for (n = 0; n < KEY_DELAY; n++)
-                       asm("nop");
-       }
-       post_out_buff("\b2\0");
-
-       for (i = 0; i < KEY_LOOP; i++) {
-               value = *pPORTFIO & PF5;
-               if (*pUART0_RBR == 0x0D) {
-                       value = 0;
-                       goto key_pressed;
-               }
-               if (value != 0)
-                       goto key_pressed;
-               for (n = 0; n < KEY_DELAY; n++)
-                       asm("nop");
-       }
-       post_out_buff("\b1\0");
-
-       for (i = 0; i < KEY_LOOP; i++) {
-               value = *pPORTFIO & PF5;
-               if (*pUART0_RBR == 0x0D) {
-                       value = 0;
-                       goto key_pressed;
-               }
-               if (value != 0)
-                       goto key_pressed;
-               for (n = 0; n < KEY_DELAY; n++)
-                       asm("nop");
-       }
-      key_pressed:
-       post_out_buff("\b0");
-       post_out_buff("\n\r\0");
-       if (value == 0)
-               return 0;
-       post_out_buff("Hotkey has been pressed, Enter POST . . . . . .\n\r\0");
-       return 1;
-}
-
 void post_init_pll(int mult, int div)
 {
 
-       *pSIC_IWR = 0x01;
-       *pPLL_CTL = (mult << 9);
-       *pPLL_DIV = div;
+       bfin_write_SIC_IWR(0x01);
+       bfin_write_PLL_CTL((mult << 9));
+       bfin_write_PLL_DIV(div);
        asm("CLI R2;");
        asm("IDLE;");
        asm("STI R2;");
-       while (!(*pPLL_STAT & 0x20)) ;
+       while (!(bfin_read_PLL_STAT() & 0x20)) ;
 }
 
 int post_init_sdram(int sclk)
@@ -304,18 +241,17 @@ int post_init_sdram(int sclk)
 
        SSYNC();
 
-       *pEBIU_SDGCTL |= 0x1000000;
+       bfin_write_EBIU_SDGCTL(bfin_write_EBIU_SDGCTL() | 0x1000000);
        /* Set the SDRAM Refresh Rate control register based on SSCLK value */
-       *pEBIU_SDRRC = mem_SDRRC;
+       bfin_write_EBIU_SDRRC(mem_SDRRC);
 
        /* SDRAM Memory Bank Control Register */
-       *pEBIU_SDBCTL = mem_SDBCTL;
+       bfin_write_EBIU_SDBCTL(mem_SDBCTL);
 
        /* SDRAM Memory Global Control Register */
-       *pEBIU_SDGCTL = mem_SDGCTL;
+       bfin_write_EBIU_SDGCTL(mem_SDGCTL);
        SSYNC();
        return mem_SDRRC;
 }
 
 #endif                         /* CONFIG_POST & CONFIG_SYS_POST_MEMORY */
-#endif                         /* CONFIG_POST */