tools: add kwboot binary to .gitignore file

[u-boot] / board / c2mon / c2mon.c

diff --git a/board/c2mon/c2mon.c b/board/c2mon/c2mon.c
index ca8eb0cb02bbddec7839acf5eb511772fcbd6198..348dfa0af36d6d60af48e99a48aafef5f7666184 100644 (file)
--- a/board/c2mon/c2mon.c
+++ b/board/c2mon/c2mon.c
@@ -91,14 +91,16 @@ const uint sdram_table[] =
 
 int checkboard (void)
 {
-       unsigned char *s = (unsigned char *)getenv ("serial#");
+       char buf[64];
+       int i;
+       int l = getenv_f("serial#", buf, sizeof(buf));
 
        puts ("Board: TTTech C2MON ");
 
-       for (; s && *s; ++s) {
-               if (*s == ' ')
+       for (i = 0; i < l;  ++i) {
+               if (buf[i] == ' ')
                        break;
-               putc (*s);
+               putc (buf[i]);
        }
 
        putc ('\n');
@@ -108,9 +110,9 @@ int checkboard (void)
 
 /* ------------------------------------------------------------------------- */
 
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
 {
-       volatile immap_t *immap = (immap_t *) CFG_IMMR;
+       volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
        volatile memctl8xx_t *memctl = &immap->im_memctl;
        unsigned long reg;
        long int size8, size9;
@@ -124,17 +126,17 @@ long int initdram (int board_type)
         * with two SDRAM banks or four cycles every 31.2 us with one
         * bank. It will be adjusted after memory sizing.
         */
-       memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+       memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
 
        memctl->memc_mar = 0x00000088;
 
        /*
         * Map controller bank 2 the SDRAM bank 2 at physical address 0.
         */
-       memctl->memc_or2 = CFG_OR2_PRELIM;
-       memctl->memc_br2 = CFG_BR2_PRELIM;
+       memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
+       memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
 
-       memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));     /* no refresh yet */
+       memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));      /* no refresh yet */
 
        udelay (200);
 
@@ -154,7 +156,7 @@ long int initdram (int board_type)
         *
         * try 8 column mode
         */
-       size8 = dram_size (CFG_MAMR_8COL,
+       size8 = dram_size (CONFIG_SYS_MAMR_8COL,
                           SDRAM_BASE2_PRELIM,
                           SDRAM_MAX_SIZE);
 
@@ -163,7 +165,7 @@ long int initdram (int board_type)
        /*
         * try 9 column mode
         */
-       size9 = dram_size (CFG_MAMR_9COL,
+       size9 = dram_size (CONFIG_SYS_MAMR_9COL,
                           SDRAM_BASE2_PRELIM,
                           SDRAM_MAX_SIZE);
 
@@ -172,7 +174,7 @@ long int initdram (int board_type)
 /*             debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);  */
        } else {                        /* back to 8 columns            */
                size = size8;
-               memctl->memc_mamr = CFG_MAMR_8COL;
+               memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
                udelay (500);
 /*             debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);  */
        }
@@ -185,15 +187,15 @@ long int initdram (int board_type)
         */
        if (size < 0x02000000) {
                /* reduce to 15.6 us (62.4 us / quad) */
-               memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+               memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
                udelay (1000);
        }
 
        /*
         * Final mapping
         */
-       memctl->memc_or2 = ((-size) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
-       memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+       memctl->memc_or2 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+       memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 
        /*
         * No bank 1
@@ -204,7 +206,7 @@ long int initdram (int board_type)
 
        /* adjust refresh rate depending on SDRAM type, one bank */
        reg = memctl->memc_mptpr;
-       reg >>= 1;                      /* reduce to CFG_MPTPR_1BK_8K / _4K */
+       reg >>= 1;                      /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
        memctl->memc_mptpr = reg;
 
        udelay (10000);
@@ -225,7 +227,7 @@ long int initdram (int board_type)
 static long int dram_size (long int mamr_value, long int *base,
                                                   long int maxsize)
 {
-       volatile immap_t *immap = (immap_t *) CFG_IMMR;
+       volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
        volatile memctl8xx_t *memctl = &immap->im_memctl;
 
        memctl->memc_mamr = mamr_value;