int checkboard (void)
{
- unsigned char *s = getenv ("serial#");
+ unsigned char *s = (unsigned char *)getenv ("serial#");
puts ("Board: TTTech C2MON ");
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
unsigned long reg;
long int size8, size9;
* with two SDRAM banks or four cycles every 31.2 us with one
* bank. It will be adjusted after memory sizing.
*/
- memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+ memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
memctl->memc_mar = 0x00000088;
/*
* Map controller bank 2 the SDRAM bank 2 at physical address 0.
*/
- memctl->memc_or2 = CFG_OR2_PRELIM;
- memctl->memc_br2 = CFG_BR2_PRELIM;
+ memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
+ memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
- memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
+ memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
udelay (200);
*
* try 8 column mode
*/
- size8 = dram_size (CFG_MAMR_8COL,
- (ulong *)SDRAM_BASE2_PRELIM,
+ size8 = dram_size (CONFIG_SYS_MAMR_8COL,
+ SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
udelay (1000);
/*
* try 9 column mode
*/
- size9 = dram_size (CFG_MAMR_9COL,
- (ulong *) SDRAM_BASE2_PRELIM,
+ size9 = dram_size (CONFIG_SYS_MAMR_9COL,
+ SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
if (size8 < size9) { /* leave configuration at 9 columns */
/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
} else { /* back to 8 columns */
size = size8;
- memctl->memc_mamr = CFG_MAMR_8COL;
+ memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
udelay (500);
/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
}
*/
if (size < 0x02000000) {
/* reduce to 15.6 us (62.4 us / quad) */
- memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+ memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
udelay (1000);
}
/*
* Final mapping
*/
- memctl->memc_or2 = ((-size) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
- memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+ memctl->memc_or2 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+ memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
/*
* No bank 1
/* adjust refresh rate depending on SDRAM type, one bank */
reg = memctl->memc_mptpr;
- reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
+ reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
memctl->memc_mptpr = reg;
udelay (10000);
static long int dram_size (long int mamr_value, long int *base,
long int maxsize)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
- volatile long int *addr;
- ulong cnt, val, size;
- ulong save[32]; /* to make test non-destructive */
- unsigned char i = 0;
memctl->memc_mamr = mamr_value;
- for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- /* write 0 to base address */
- addr = base;
- save[i] = *addr;
- *addr = 0;
-
- /* check at base address */
- if ((val = *addr) != 0) {
- /* Restore the original data before leaving the function.
- */
- *addr = save[i];
- for (cnt = 1; cnt <= maxsize / sizeof(long); cnt <<= 1) {
- addr = (volatile ulong *) base + cnt;
- *addr = save[--i];
- }
- return (0);
- }
-
- for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
-
- val = *addr;
- *addr = save[--i];
-
- if (val != (~cnt)) {
- size = cnt * sizeof (long);
- /* Restore the original data before returning
- */
- for (cnt <<= 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
- addr = (volatile ulong *) base + cnt;
- *addr = save[--i];
- }
- return (size);
- }
- }
- return (maxsize);
+ return (get_ram_size(base, maxsize));
}