]> git.sur5r.net Git - u-boot/blobdiff - board/cradle/cradle.c
nds32: asm/io.h: add __iormb __iowmb and inline io support
[u-boot] / board / cradle / cradle.c
index c4a93f91b76bc2df4c84e0894d49e97f230e7c45..2bbf2d532d43adf05cd1e3195e83ac6da3507f8a 100644 (file)
@@ -185,6 +185,10 @@ int
 board_init (void)
 /**********************************************************/
 {
+       /* We have RAM, disable cache */
+       dcache_disable();
+       icache_disable();
+
        led_code (0xf, YELLOW);
 
        /* arch number of HHP Cradle */
@@ -206,24 +210,18 @@ board_init (void)
        return 1;
 }
 
-int
-/**********************************************************/
-dram_init (void)
-/**********************************************************/
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+       pxa_dram_init();
+       gd->ram_size = PHYS_SDRAM_1_SIZE;
+       return 0;
+}
+
+void dram_init_banksize(void)
 {
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-       gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
-       gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-       gd->bd->bi_dram[1].size  = PHYS_SDRAM_2_SIZE;
-       gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-       gd->bd->bi_dram[2].size  = PHYS_SDRAM_3_SIZE;
-       gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
-       gd->bd->bi_dram[3].size  = PHYS_SDRAM_4_SIZE;
-
-       return (PHYS_SDRAM_1_SIZE +
-               PHYS_SDRAM_2_SIZE +
-               PHYS_SDRAM_3_SIZE +
-               PHYS_SDRAM_4_SIZE );
+       gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 }
 
 #ifdef CONFIG_CMD_NET