at91rm9200: fix lowlevel_init() SMRDATA size

[u-boot] / board / cradle / cradle.c

diff --git a/board/cradle/cradle.c b/board/cradle/cradle.c
index f599a315aebcfdabcae839b8fab515afd43faad8..2bbf2d532d43adf05cd1e3195e83ac6da3507f8a 100644 (file)
--- a/board/cradle/cradle.c
+++ b/board/cradle/cradle.c
@@ -27,6 +27,10 @@
 
 #include <asm/arch/pxa-regs.h>
 #include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 /* ------------------------------------------------------------------------- */
 
@@ -89,8 +93,8 @@ set_led (int led, int color)
        int shift = led * 2;
        unsigned long mask = 0x3 << shift;
 
-       CRADLE_LED_CLR_REG = mask;      /* clear bits */
-       CRADLE_LED_SET_REG = (color << shift);  /* set bits */
+       writel(mask, GPCR2);    /* clear bits */
+       writel((color << shift), GPSR2);        /* set bits */
        udelay (5000);
 }
 
@@ -170,7 +174,7 @@ init_sio (int led, unsigned long base)
 
 int
 /**********************************************************/
-board_post_init (void)
+board_late_init (void)
 /**********************************************************/
 {
        return (0);
@@ -181,12 +185,14 @@ int
 board_init (void)
 /**********************************************************/
 {
-       DECLARE_GLOBAL_DATA_PTR;
+       /* We have RAM, disable cache */
+       dcache_disable();
+       icache_disable();
 
        led_code (0xf, YELLOW);
 
        /* arch number of HHP Cradle */
-       gd->bd->bi_arch_number = 174;
+       gd->bd->bi_arch_number = MACH_TYPE_HHP_CRADLE;
 
        /* adress of boot parameters */
        gd->bd->bi_boot_params = 0xa0000100;
@@ -204,24 +210,27 @@ board_init (void)
        return 1;
 }
 
-int
-/**********************************************************/
-dram_init (void)
-/**********************************************************/
+extern void pxa_dram_init(void);
+int dram_init(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
+       pxa_dram_init();
+       gd->ram_size = PHYS_SDRAM_1_SIZE;
+       return 0;
+}
 
+void dram_init_banksize(void)
+{
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-       gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
-       gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-       gd->bd->bi_dram[1].size  = PHYS_SDRAM_2_SIZE;
-       gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-       gd->bd->bi_dram[2].size  = PHYS_SDRAM_3_SIZE;
-       gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
-       gd->bd->bi_dram[3].size  = PHYS_SDRAM_4_SIZE;
-
-       return (PHYS_SDRAM_1_SIZE +
-               PHYS_SDRAM_2_SIZE +
-               PHYS_SDRAM_3_SIZE +
-               PHYS_SDRAM_4_SIZE );
+       gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+       int rc = 0;
+#ifdef CONFIG_SMC91111
+       rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+       return rc;
 }
+#endif