Merge branch 'next' of git://git.denx.de/u-boot-mpc83xx

[u-boot] / board / cray / L1 / init.S

diff --git a/board/cray/L1/init.S b/board/cray/L1/init.S
index 4b6b3f400303bb1fdb7803debc49a80081eb4847..44c688d1f0436b88f7cc951d529bd2c9b79f2be9 100644 (file)
--- a/board/cray/L1/init.S
+++ b/board/cray/L1/init.S
@@ -1,23 +1,6 @@
-/*------------------------------------------------------------------------------+ */
-/* */
-/*       This source code has been made available to you by IBM on an AS-IS */
-/*       basis.  Anyone receiving this source is licensed under IBM */
-/*       copyrights to use it in any way he or she deems fit, including */
-/*       copying it, modifying it, compiling it, and redistributing it either */
-/*       with or without modifications.  No license under IBM patents or */
-/*       patent applications is to be implied by the copyright license. */
-/* */
-/*       Any user of this software should understand that IBM cannot provide */
-/*       technical support for this software and will not be responsible for */
-/*       any consequences resulting from the use of this software. */
-/* */
-/*       Any person who transfers this source code or any derivative work */
-/*       must include the IBM copyright notice, this paragraph, and the */
-/*       preceding two paragraphs in the transferred software. */
-/* */
-/*       COPYRIGHT   I B M   CORPORATION 1995 */
-/*       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M */
-/*------------------------------------------------------------------------------- */
+/*
+ * SPDX-License-Identifier:    GPL-2.0 IBM-pibs
+ */
 
 /*----------------------------------------------------------------------------- */
 /* Function:     ext_bus_cntlr_init */
@@ -37,7 +20,7 @@
 /*     Bank 6 - not used */
 /*     Bank 7 - FPGA registers */
 /*-----------------------------------------------------------------------------#include <config.h> */
-#include <ppc4xx.h>
+#include <asm/ppc4xx.h>
 
 #define _LINUX_CONFIG_H 1      /* avoid reading Linux autoconf.h file  */
 
@@ -83,17 +66,17 @@ ext_bus_cntlr_init:
        /* Peripheral Bank 0 (Flash) initialization */
        /*---------------------------------------------------------------------- */
                /* 0x7F8FFE80 slowest boot */
-       addi    r4,0,pb0ap
-       mtdcr   ebccfga,r4
+       addi    r4,0,PB1AP
+       mtdcr   EBC0_CFGADDR,r4
        addis   r4,0,0x9B01
        ori     r4,r4,0x5480
-       mtdcr   ebccfgd,r4
+       mtdcr   EBC0_CFGDATA,r4
 
-       addi    r4,0,pb0cr
-       mtdcr   ebccfga,r4
+       addi    r4,0,PB0CR
+       mtdcr   EBC0_CFGADDR,r4
        addis   r4,0,0xFFC5           /* BAS=0xFFC,BS=0x4(4MB),BU=0x3(R/W), */
        ori     r4,r4,0x8000          /* BW=0x0( 8 bits) */
-       mtdcr   ebccfgd,r4
+       mtdcr   EBC0_CFGDATA,r4
 
        blr
 
@@ -121,16 +104,16 @@ ext_bus_cntlr_init:
                /* all reserved bits=0 */
        /*---------------------------------------------------------------------- */
        /*---------------------------------------------------------------------- */
-       addi    r4,0,pb1ap
-       mtdcr   ebccfga,r4
+       addi    r4,0,PB1AP
+       mtdcr   EBC0_CFGADDR,r4
        addis   r4,0,0x0185             /* hiword */
        ori     r4,r4,0x4380    /* loword */
-       mtdcr   ebccfgd,r4
+       mtdcr   EBC0_CFGDATA,r4
 
-       addi    r4,0,pb1cr
-       mtdcr   ebccfga,r4
+       addi    r4,0,PB1CR
+       mtdcr   EBC0_CFGADDR,r4
        addis   r4,0,0xF001           /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W), */
        ori     r4,r4,0x8000          /* BW=0x0( 8 bits) */
-       mtdcr   ebccfgd,r4
+       mtdcr   EBC0_CFGDATA,r4
 
        blr