Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

[u-boot] / board / csb272 / csb272.c

diff --git a/board/csb272/csb272.c b/board/csb272/csb272.c
index 5a585ae37f79398f65fbfae31c4598c7a2bf6780..d6d65cf45cf9b30c6fd937c462c9de3b1380993d 100644 (file)
--- a/board/csb272/csb272.c
+++ b/board/csb272/csb272.c
@@ -51,9 +51,9 @@ uchar pll_fs6377_regs[16] = {
  */
 int pll_init(void)
 {
-       i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+       i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 
-       return  i2c_write(CFG_I2C_PLL_ADDR, 0, 1,
+       return  i2c_write(CONFIG_SYS_I2C_PLL_ADDR, 0, 1,
                (uchar *) pll_fs6377_regs, sizeof(pll_fs6377_regs));
 }
 
@@ -87,15 +87,15 @@ int board_early_init_f(void)
    |
    +-------------------------------------------------------------------------*/
 
-       mtdcr (uicsr, 0xFFFFFFFF);   /* clear all ints */
-       mtdcr (uicer, 0x00000000);   /* disable all ints */
-       mtdcr (uiccr, 0x00000000);   /* set all to be non-critical */
-       mtdcr (uicpr, 0xFFFFFF83);   /* set int polarities */
-       mtdcr (uictr, 0x10000000);   /* set int trigger levels */
-       mtdcr (uicvcr, 0x00000001);  /* set vect base=0,INT0 highest priority */
-       mtdcr (uicsr, 0xFFFFFFFF);   /* clear all ints */
+       mtdcr (UIC0SR, 0xFFFFFFFF);   /* clear all ints */
+       mtdcr (UIC0ER, 0x00000000);   /* disable all ints */
+       mtdcr (UIC0CR, 0x00000000);   /* set all to be non-critical */
+       mtdcr (UIC0PR, 0xFFFFFF83);   /* set int polarities */
+       mtdcr (UIC0TR, 0x10000000);   /* set int trigger levels */
+       mtdcr (UIC0VCR, 0x00000001);  /* set vect base=0,INT0 highest priority */
+       mtdcr (UIC0SR, 0xFFFFFFFF);   /* clear all ints */
 
-       mtebc (epcr, 0xa8400000);   /* EBC always driven */
+       mtebc (EBC0_CFG, 0xa8400000);   /* EBC always driven */
 
        return 0; /* success */
 }
@@ -135,29 +135,29 @@ phys_size_t initdram (int board_type)
 
        tot_size = 0;
 
-       mtdcr (memcfga, mem_mb0cf);
-       tmp = mfdcr (memcfgd);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
+       tmp = mfdcr (SDRAM0_CFGDATA);
        if (tmp & 0x00000001) {
                bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
                tot_size += bank_size;
        }
 
-       mtdcr (memcfga, mem_mb1cf);
-       tmp = mfdcr (memcfgd);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
+       tmp = mfdcr (SDRAM0_CFGDATA);
        if (tmp & 0x00000001) {
                bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
                tot_size += bank_size;
        }
 
-       mtdcr (memcfga, mem_mb2cf);
-       tmp = mfdcr (memcfgd);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
+       tmp = mfdcr (SDRAM0_CFGDATA);
        if (tmp & 0x00000001) {
                bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
                tot_size += bank_size;
        }
 
-       mtdcr (memcfga, mem_mb3cf);
-       tmp = mfdcr (memcfgd);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
+       tmp = mfdcr (SDRAM0_CFGDATA);
        if (tmp & 0x00000001) {
                bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
                tot_size += bank_size;