blackfin: add bf6xx spi driver

[u-boot] / board / csb472 / csb472.c

diff --git a/board/csb472/csb472.c b/board/csb472/csb472.c
index 0c7760a02f8c419b82d7959554f338188ec4dcf8..eac440848ab15951a24c41a394e66d7c508f14f2 100644 (file)
--- a/board/csb472/csb472.c
+++ b/board/csb472/csb472.c
@@ -25,7 +25,7 @@
 #include <asm/processor.h>
 #include <i2c.h>
 #include <miiphy.h>
-#include <ppc4xx_enet.h>
+#include <asm/ppc4xx-emac.h>
 
 void sdram_init(void);
 
@@ -97,34 +97,34 @@ phys_size_t initdram (int board_type)
        /*
         * ToDo: Move the asm init routine sdram_init() to this C file,
         * or even better use some common ppc4xx code available
-        * in cpu/ppc4xx
+        * in arch/powerpc/cpu/ppc4xx
         */
        sdram_init();
 
        tot_size = 0;
 
-       mtdcr (SDRAM0_CFGADDR, mem_mb0cf);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
        tmp = mfdcr (SDRAM0_CFGDATA);
        if (tmp & 0x00000001) {
                bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
                tot_size += bank_size;
        }
 
-       mtdcr (SDRAM0_CFGADDR, mem_mb1cf);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
        tmp = mfdcr (SDRAM0_CFGDATA);
        if (tmp & 0x00000001) {
                bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
                tot_size += bank_size;
        }
 
-       mtdcr (SDRAM0_CFGADDR, mem_mb2cf);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
        tmp = mfdcr (SDRAM0_CFGDATA);
        if (tmp & 0x00000001) {
                bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
                tot_size += bank_size;
        }
 
-       mtdcr (SDRAM0_CFGADDR, mem_mb3cf);
+       mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
        tmp = mfdcr (SDRAM0_CFGDATA);
        if (tmp & 0x00000001) {
                bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
@@ -144,11 +144,11 @@ int last_stage_init(void)
        miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR);
 
        /* AUTO neg */
-       miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_BMCR,
-                       PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+       miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_BMCR,
+                       BMCR_ANENABLE | BMCR_ANRESTART);
 
        /* LEDs     */
-       miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08);
+       miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_NWAYTEST, 0x0d08);
 
        return 0; /* success */
 }