clk: Add Actions Semi OWL clock support

[u-boot] / board / dbau1x00 / dbau1x00.c

diff --git a/board/dbau1x00/dbau1x00.c b/board/dbau1x00/dbau1x00.c
index 3b6fcec1c8a61151d024f46402997c62856ef328..1e62753b30fea5f528934c60ee028d72fc0292d7 100644 (file)
--- a/board/dbau1x00/dbau1x00.c
+++ b/board/dbau1x00/dbau1x00.c
@@ -1,65 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2003
  * Thomas.Lange@corelatus.se
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
  */
 
 #include <common.h>
 #include <command.h>
-#include <asm/au1x00.h>
+#include <mach/au1x00.h>
 #include <asm/mipsregs.h>
+#include <asm/io.h>
 
-long int initdram(int board_type)
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
 {
        /* Sdram is setup by assembler code */
        /* If memory could be changed, we should return the true value here */
-       return 64*1024*1024;
+       gd->ram_size = MEM_SIZE * 1024 * 1024;
+
+       return 0;
 }
 
 #define BCSR_PCMCIA_PC0DRVEN           0x0010
 #define BCSR_PCMCIA_PC0RST             0x0080
 
-/* In cpu/mips/cpu.c */
+/* In arch/mips/cpu/cpu.c */
 void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
 
 int checkboard (void)
 {
+#ifdef CONFIG_IDE_PCMCIA
        u16 status;
-       volatile u32 *pcmcia_bcsr = (u32*)(DB1000_BCSR_ADDR+0x10);
-       volatile u32 *phy = (u32*)(DB1000_BCSR_ADDR+0xC);
+       volatile u32 *pcmcia_bcsr = (u32*)(DB1XX0_BCSR_ADDR+0x10);
+#endif /* CONFIG_IDE_PCMCIA */
+       volatile u32 *phy = (u32*)(DB1XX0_BCSR_ADDR+0xC);
        volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
        u32 proc_id;
 
        *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
 
-       proc_id = read_32bit_cp0_register(CP0_PRID);
+       proc_id = read_c0_prid();
 
-       switch(proc_id>>24){
+       switch (proc_id >> 24) {
        case 0:
-         puts("Board: Merlot (DbAu1000)\n");
-         printf("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n",
-                (proc_id>>8)&0xFF,proc_id&0xFF);
-         break;
+               puts ("Board: Merlot (DbAu1000)\n");
+               printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n",
+                       (proc_id >> 8) & 0xFF, proc_id & 0xFF);
+               break;
+       case 1:
+               puts ("Board: DbAu1500\n");
+               printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x\n",
+                       (proc_id >> 8) & 0xFF, proc_id & 0xFF);
+               break;
+       case 2:
+               puts ("Board: DbAu1100\n");
+               printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n",
+                       (proc_id >> 8) & 0xFF, proc_id & 0xFF);
+               break;
+       case 3:
+               puts ("Board: DbAu1550\n");
+               printf ("CPU: Au1550, id: 0x%02x, rev: 0x%02x\n",
+                       (proc_id >> 8) & 0xFF, proc_id & 0xFF);
+               break;
        default:
-         printf("Unsupported cpu %d, proc_id=0x%x\n",proc_id>>24,proc_id);
+               printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
        }
+
+       set_io_port_base(0);
+
 #ifdef CONFIG_IDE_PCMCIA
        /* Enable 3.3 V on slot 0 ( VCC )
           No 5V */
@@ -85,26 +93,26 @@ int checkboard (void)
        /* We dont need theese unless we run whole pcmcia package */
        write_one_tlb(20,                 /* index */
                      0x01ffe000,         /* Pagemask, 16 MB pages */
-                     CFG_PCMCIA_IO_BASE, /* Hi */
+                     CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */
                      0x3C000017,         /* Lo0 */
                      0x3C200017);        /* Lo1 */
 
        write_one_tlb(21,                   /* index */
                      0x01ffe000,           /* Pagemask, 16 MB pages */
-                     CFG_PCMCIA_ATTR_BASE, /* Hi */
+                     CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */
                      0x3D000017,           /* Lo0 */
                      0x3D200017);          /* Lo1 */
-#endif
+#endif /* 0 */
        write_one_tlb(22,                   /* index */
                      0x01ffe000,           /* Pagemask, 16 MB pages */
-                     CFG_PCMCIA_MEM_ADDR,  /* Hi */
+                     CONFIG_SYS_PCMCIA_MEM_ADDR,  /* Hi */
                      0x3E000017,           /* Lo0 */
                      0x3E200017);          /* Lo1 */
+#endif /* CONFIG_IDE_PCMCIA */
 
        /* Release reset of ethernet PHY chips */
        /* Always do this, because linux does not know about it */
        *phy = 3;
 
        return 0;
-#endif
 }