Merge branch 'master' of git://git.denx.de/u-boot-arm

[u-boot] / board / dbau1x00 / lowlevel_init.S

diff --git a/board/dbau1x00/lowlevel_init.S b/board/dbau1x00/lowlevel_init.S
index 7afd5840c8628a6925e0067035ea2d6c79d15656..842fb76e5873e768d0a11b518ecb0aa3a4cacf8a 100644 (file)
--- a/board/dbau1x00/lowlevel_init.S
+++ b/board/dbau1x00/lowlevel_init.S
@@ -1,7 +1,6 @@
 /* Memory sub-system initialization code */
 
 #include <config.h>
-#include <version.h>
 #include <asm/regdef.h>
 #include <asm/au1x00.h>
 #include <asm/mipsregs.h>
@@ -9,8 +8,8 @@
 #define AU1500_SYS_ADDR                0xB1900000
 #define sys_endian             0x0038
 #define CP0_Config0            $16
-#define CPU_SCALE              ((CFG_MHZ) / 12) /* CPU clock is a multiple of 12 MHz */
-#define MEM_1MS                        ((CFG_MHZ) * 1000)
+#define CPU_SCALE              ((CONFIG_SYS_MHZ) / 12) /* CPU clock is a multiple of 12 MHz */
+#define MEM_1MS                        ((CONFIG_SYS_MHZ) * 1000)
 
        .text
        .set noreorder
@@ -185,6 +184,8 @@ tlbloop:
        bne     t0, t2, tlbloop
        nop
 
+#endif /* CONFIG_DBAU1550 */
+
        /* First setup pll:s to make serial work ok */
        /* We have a 12 MHz crystal */
        li      t0, SYS_CPUPLL
@@ -205,6 +206,7 @@ tlbloop:
        sw      t1, 0(t0) /* aux pll */
        sync
 
+#ifdef CONFIG_DBAU1550
        /*  Static memory controller */
        /* RCE0 - can not change while fetching, do so from icache */
        move            t2, ra /* Store return address */
@@ -237,7 +239,7 @@ noCacheJump:
        sw      t1, 0(t0)
 #else /* CONFIG_DBAU1550 */
        li      t0, MEM_STTIME0
-       li      t1, 0x00014C0F
+       li      t1, 0x040181D7
        sw      t1, 0(t0)
 
        /* RCE0 AMD 29LV640M MirrorBit Flash */
@@ -583,5 +585,5 @@ noCacheJump:
        sw      t1, 0(t0)
        sync
 
-       j       ra
+       jr      ra
        nop