/*
- * (C) Copyright 2001
+ * (C) Copyright 2001-2003
* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
#define MAX_ONES 226
-#define IBM405GP_GPIO0_OR 0xef600700 /* GPIO Output */
-#define IBM405GP_GPIO0_TCR 0xef600704 /* GPIO Three-State Control */
-#define IBM405GP_GPIO0_ODR 0xef600718 /* GPIO Open Drain */
-#define IBM405GP_GPIO0_IR 0xef60071c /* GPIO Input */
-
#ifdef CFG_FPGA_PRG
# define FPGA_PRG CFG_FPGA_PRG /* FPGA program pin (ppc output)*/
# define FPGA_CLK CFG_FPGA_CLK /* FPGA clk pin (ppc output) */
#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */
#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */
-#define SET_FPGA(data) out32(IBM405GP_GPIO0_OR, data)
+#define SET_FPGA(data) out32(GPIO0_OR, data)
#define FPGA_WRITE_1 { \
- SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
- SET_FPGA(FPGA_PRG | FPGA_DATA); /* set data to 1 */ \
- SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set clock to 1 */ \
- SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
+ SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
+ SET_FPGA(FPGA_PRG | FPGA_DATA); /* set data to 1 */ \
+ SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set clock to 1 */ \
+ SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
#define FPGA_WRITE_0 { \
- SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
- SET_FPGA(FPGA_PRG); /* set data to 0 */ \
- SET_FPGA(FPGA_PRG | FPGA_CLK); /* set clock to 1 */ \
- SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
+ SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
+ SET_FPGA(FPGA_PRG); /* set data to 0 */ \
+ SET_FPGA(FPGA_PRG | FPGA_CLK); /* set clock to 1 */ \
+ SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
static int fpga_boot(unsigned char *fpgadata, int size)
while (1)
{
if ((fpgadata[index] == 0xff) && (fpgadata[index+1] == 0xff) &&
- (fpgadata[index+2] == 0xff) && (fpgadata[index+3] == 0xff))
- break; /* preamble found */
+ (fpgadata[index+2] == 0xff) && (fpgadata[index+3] == 0xff))
+ break; /* preamble found */
else
- index++;
+ index++;
}
#else
/* search for preamble 0xFF2X */
/*
* Setup port pins for fpga programming
*/
- out32(IBM405GP_GPIO0_ODR, 0x00000000); /* no open drain pins */
- out32(IBM405GP_GPIO0_TCR, FPGA_PRG | FPGA_CLK | FPGA_DATA); /* setup for output */
- out32(IBM405GP_GPIO0_OR, FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set output pins to high */
+ out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
+ out32(GPIO0_TCR, in32(GPIO0_TCR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* setup for output */
+ out32(GPIO0_OR, in32(GPIO0_OR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set pins to high */
- DBG("%s, ",((in32(IBM405GP_GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE" );
- DBG("%s\n",((in32(IBM405GP_GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT" );
+ DBG("%s, ",((in32(GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE" );
+ DBG("%s\n",((in32(GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT" );
/*
* Init fpga by asserting and deasserting PROGRAM*
/* Wait for FPGA init line low */
count = 0;
- while (in32(IBM405GP_GPIO0_IR) & FPGA_INIT)
+ while (in32(GPIO0_IR) & FPGA_INIT)
{
udelay(1000); /* wait 1ms */
/* Check for timeout - 100us max, so use 3ms */
if (count++ > 3)
- {
- DBG("FPGA: Booting failed!\n");
- return ERROR_FPGA_PRG_INIT_LOW;
- }
+ {
+ DBG("FPGA: Booting failed!\n");
+ return ERROR_FPGA_PRG_INIT_LOW;
+ }
}
- DBG("%s, ",((in32(IBM405GP_GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE" );
- DBG("%s\n",((in32(IBM405GP_GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT" );
+ DBG("%s, ",((in32(GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE" );
+ DBG("%s\n",((in32(GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT" );
/* deassert PROGRAM* */
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
/* Wait for FPGA end of init period . */
count = 0;
- while (!(in32(IBM405GP_GPIO0_IR) & FPGA_INIT))
+ while (!(in32(GPIO0_IR) & FPGA_INIT))
{
udelay(1000); /* wait 1ms */
/* Check for timeout */
if (count++ > 3)
- {
- DBG("FPGA: Booting failed!\n");
- return ERROR_FPGA_PRG_INIT_HIGH;
- }
+ {
+ DBG("FPGA: Booting failed!\n");
+ return ERROR_FPGA_PRG_INIT_HIGH;
+ }
}
- DBG("%s, ",((in32(IBM405GP_GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE" );
- DBG("%s\n",((in32(IBM405GP_GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT" );
+ DBG("%s, ",((in32(GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE" );
+ DBG("%s\n",((in32(GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT" );
DBG("write configuration data into fpga\n");
/* write configuration-data into fpga... */
for (i=index; i<size; i++)
{
for (j=0; j<8; j++)
- {
- if ((fpgadata[i] & 0x80) == 0x80)
+ {
+ if ((fpgadata[i] & 0x80) == 0x80)
{
- FPGA_WRITE_1;
+ FPGA_WRITE_1;
}
- else
+ else
{
- FPGA_WRITE_0;
+ FPGA_WRITE_0;
}
- fpgadata[i] <<= 1;
- }
+ fpgadata[i] <<= 1;
+ }
}
#else
/* send 0xff 0x20 */
if ((b >= 1) && (b <= MAX_ONES))
{
for(bit=0; bit<b; bit++)
- {
- FPGA_WRITE_1;
- }
+ {
+ FPGA_WRITE_1;
+ }
FPGA_WRITE_0;
}
else if (b == (MAX_ONES+1))
{
for(bit=1; bit<b; bit++)
- {
- FPGA_WRITE_1;
- }
+ {
+ FPGA_WRITE_1;
+ }
}
else if ((b >= (MAX_ONES+2)) && (b <= 254))
{
for(bit=0; bit<(b-(MAX_ONES+2)); bit++)
- {
- FPGA_WRITE_0;
- }
- FPGA_WRITE_1;
+ {
+ FPGA_WRITE_0;
+ }
+ FPGA_WRITE_1;
}
else if (b == 255)
- {
- FPGA_WRITE_1;
- }
+ {
+ FPGA_WRITE_1;
+ }
}
#endif
- DBG("%s, ",((in32(IBM405GP_GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE" );
- DBG("%s\n",((in32(IBM405GP_GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT" );
+ DBG("%s, ",((in32(GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE" );
+ DBG("%s\n",((in32(GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT" );
/*
* Check if fpga's DONE signal - correctly booted ?
/* Wait for FPGA end of programming period . */
count = 0;
- while (!(in32(IBM405GP_GPIO0_IR) & FPGA_DONE))
+ while (!(in32(GPIO0_IR) & FPGA_DONE))
{
udelay(1000); /* wait 1ms */
/* Check for timeout */
if (count++ > 3)
- {
- DBG("FPGA: Booting failed!\n");
- return ERROR_FPGA_PRG_DONE;
- }
+ {
+ DBG("FPGA: Booting failed!\n");
+ return ERROR_FPGA_PRG_DONE;
+ }
}
DBG("FPGA: Booting successful!\n");
projects / u-boot / blobdiff