*/
#include <common.h>
+#include <command.h>
#include <74xx_7xx.h>
#include "../../Marvell/include/memory.h"
#include "../../Marvell/include/pci.h"
extern void flush_data_cache (void);
extern void invalidate_l1_instruction_cache (void);
+extern flash_info_t flash_info[];
/* ------------------------------------------------------------------------- */
/* disable the dcache and MMU */
dcache_lock ();
#endif
+ if (flash_info[3].size < CFG_FLASH_INCREMENT) {
+ unsigned int flash_offset;
+ unsigned int l;
+
+ flash_offset = CFG_FLASH_INCREMENT - flash_info[3].size;
+ for (l = 0; l < CFG_MAX_FLASH_SECT; l++) {
+ if (flash_info[3].start[l] != 0) {
+ flash_info[3].start[l] += flash_offset;
+ }
+ }
+ flash_protect (FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE + monitor_flash_len - 1,
+ &flash_info[3]);
+ }
return 0;
}
{
asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
"stfd 0, 0(4)" /* *dest = fpr0 */
- : : : "fr0"); /* Clobbers fr0 */
+ : : : "fr0"); /* Clobbers fr0 */
return;
}
#if defined (CFG_DRAM_TEST_DATA)
unsigned long long pattern[] = {
- 0xaaaaaaaaaaaaaaaa,
- 0xcccccccccccccccc,
- 0xf0f0f0f0f0f0f0f0,
- 0xff00ff00ff00ff00,
- 0xffff0000ffff0000,
- 0xffffffff00000000,
- 0x00000000ffffffff,
- 0x0000ffff0000ffff,
- 0x00ff00ff00ff00ff,
- 0x0f0f0f0f0f0f0f0f,
- 0x3333333333333333,
- 0x5555555555555555
+ 0xaaaaaaaaaaaaaaaaLL,
+ 0xccccccccccccccccLL,
+ 0xf0f0f0f0f0f0f0f0LL,
+ 0xff00ff00ff00ff00LL,
+ 0xffff0000ffff0000LL,
+ 0xffffffff00000000LL,
+ 0x00000000ffffffffLL,
+ 0x0000ffff0000ffffLL,
+ 0x00ff00ff00ff00ffLL,
+ 0x0f0f0f0f0f0f0f0fLL,
+ 0x3333333333333333LL,
+ 0x5555555555555555LL,
};
/*********************************************************************/
int mem_test_data (void)
{
unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
- unsigned long long temp64;
+ unsigned long long temp64 = 0;
int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
int i;
unsigned int hi, lo;
move64 (&(pattern[i]), pmem);
move64 (pmem, &temp64);
- /* hi = (temp64>>32) & 0xffffffff; */
- /* lo = temp64 & 0xffffffff; */
- /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
+ /* hi = (temp64>>32) & 0xffffffff; */
+ /* lo = temp64 & 0xffffffff; */
+ /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
hi = (pattern[i] >> 32) & 0xffffffff;
lo = pattern[i] & 0xffffffff;
unsigned long long wmask, short read, short write)
{
unsigned int i;
- unsigned long long temp;
+ unsigned long long temp = 0;
unsigned int hitemp, lotemp, himask, lomask;
for (i = 0; i < size; i++) {
}
#endif /* CFG_DRAM_TEST */
-/* ronen - the below functions are used by the bootm function */
+/* ronen - the below functions are used by the bootm function */
/* - we map the base register to fbe00000 (same mapping as in the LSP) */
/* - we turn off the RX gig dmas - to prevent the dma from overunning */
-/* the kernel data areas. */
-/* - we diable and invalidate the icache and dcache. */
+/* the kernel data areas. */
+/* - we diable and invalidate the icache and dcache. */
void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
{
u32 temp;
flush_data_cache ();
dcache_disable ();
}
+
+
+int do_show_cfg(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned int reset_sample_low;
+ unsigned int reset_sample_high;
+
+ GT_REG_READ(0x3c4, &reset_sample_low);
+ GT_REG_READ(0x3d4, &reset_sample_high);
+ printf("Reset configuration 0x%08x 0x%08x\n", reset_sample_low, reset_sample_high);
+
+ return(0);
+}
+
+U_BOOT_CMD(
+ show_cfg, 1, 1, do_show_cfg,
+ "show_cfg- Show Marvell strapping register\n",
+ "Show Marvell strapping register (ResetSampleLow ResetSampleHigh)\n"
+ );