74xx_7xx: CPCI750: Minor coding style cleanup of cpci750.c

[u-boot] / board / esd / cpci750 / mpsc.c

diff --git a/board/esd/cpci750/mpsc.c b/board/esd/cpci750/mpsc.c
index 52398b24ea41665c1f3cd4f66b7de9a0c29d12aa..c89426d085896be68a26889c0f6aa1af224beef0 100644 (file)
--- a/board/esd/cpci750/mpsc.c
+++ b/board/esd/cpci750/mpsc.c
@@ -42,6 +42,8 @@
 
 #include "../../Marvell/include/memory.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* Define this if you wish to use the MPSC as a register based UART.
  * This will force the serial port to not use the SDMA engine at all.
  */
@@ -157,7 +159,6 @@ char mpsc_getchar_debug (void)
  * global variables [josh] */
 int mpsc_putchar_early (char ch)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        int mpsc = CHANNEL;
        int temp =
                GTREGREAD (GALMPSC_CHANNELREG_2 + (mpsc * GALMPSC_REG_GAP));
@@ -425,8 +426,8 @@ void mpsc_sdma_init (void)
                         (MV64360_SDMA_WIN_ACCESS_FULL <<
                          (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
 
-/* Setup MPSC internal address space base address      */
-       GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS);
+/* Setup MPSC internal address space base address      */
+       GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS);
 
 /* no high address remap*/
        GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
@@ -510,16 +511,15 @@ void mpsc_init2 (void)
 
 int galbrg_set_baudrate (int channel, int rate)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        int clock;
 
        galbrg_disable (channel);       /*ok */
 
 #ifdef ZUMA_NTL
        /* from tclk */
-       clock = (CFG_TCLK / (16 * rate)) - 1;
+       clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
 #else
-       clock = (CFG_TCLK / (16 * rate)) - 1;
+       clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
 #endif
 
        galbrg_set_CDV (channel, clock);        /* set timer Reg. for BRG */