]> git.sur5r.net Git - u-boot/blobdiff - board/esd/dp405/dp405.c
twl4030: make twl4030_i2c_write_u8 prototype consistent
[u-boot] / board / esd / dp405 / dp405.c
index fc0d091bca9ecd1039f1c313fe00f7fb0a5a84ae..587809226fbcd6873588b577920b0b7668e46daa 100644 (file)
@@ -43,13 +43,13 @@ int board_early_init_f (void)
         * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
         * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
         */
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-       mtdcr(uicer, 0x00000000);       /* disable all ints */
-       mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-       mtdcr(uicpr, 0xFFFFFF80);       /* set int polarities */
-       mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-       mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+       mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+       mtdcr(UIC0PR, 0xFFFFFF80);       /* set int polarities */
+       mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+       mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+       mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 
        /*
         * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
@@ -86,7 +86,7 @@ int misc_init_r (void)
 int checkboard (void)
 {
        char str[64];
-       int i = getenv_("serial#", str, sizeof(str));
+       int i = getenv_f("serial#", str, sizeof(str));
        unsigned char trans[16] = {0x0,0x8,0x4,0xc,0x2,0xa,0x6,0xe,
                                   0x1,0x9,0x5,0xd,0x3,0xb,0x7,0xf};
        unsigned char id1, id2, rev;