u32 sdr0_pfc1, sdr0_pfc2;
u32 reg;
- mtdcr(ebccfga, xbcfg);
- mtdcr(ebccfgd, 0xb8400000);
+ mtdcr(EBC0_CFGADDR, EBC0_CFG);
+ mtdcr(EBC0_CFGDATA, 0xb8400000);
/*
* Setup the GPIO pins
mtsdr(SDR0_PFC1, sdr0_pfc1);
/* PCI arbiter enabled */
- mfsdr(sdr_pci0, reg);
- mtsdr(sdr_pci0, 0x80000000 | reg);
+ mfsdr(SDR0_PCI0, reg);
+ mtsdr(SDR0_PCI0, 0x80000000 | reg);
/* setup NAND FLASH */
mfsdr(SDR0_CUST0, sdr0_cust0);
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
- mtdcr(ebccfga, pb0cr);
- pbcr = mfdcr(ebccfgd);
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ pbcr = mfdcr(EBC0_CFGDATA);
size_val = ffs(gd->bd->bi_flashsize) - 21;
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
- mtdcr(ebccfga, pb0cr);
- mtdcr(ebccfgd, pbcr);
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ mtdcr(EBC0_CFGDATA, pbcr);
/*
* Re-check to get correct base address
* This fix will make the MAL burst disabling patch for the Linux
* EMAC driver obsolete.
*/
- reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
- mtdcr(plb4_acr, reg);
+ reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP;
+ mtdcr(PLB4_ACR, reg);
/*
* release IO-RST#
int pld_revision(void)
{
- out8(CONFIG_SYS_CPLD_BASE, 0x00);
- return (int)(in8(CONFIG_SYS_CPLD_BASE) & CPLD_VERSION_MASK);
+ out_8((void *)CONFIG_SYS_CPLD_BASE, 0x00);
+ return (int)(in_8((void *)CONFIG_SYS_CPLD_BASE) & CPLD_VERSION_MASK);
}
int board_revision(void)
* Set priority for all PLB3 devices to 0.
* Set PLB3 arbiter to fair mode.
*/
- mfsdr(sdr_amp1, addr);
- mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
- addr = mfdcr(plb3_acr);
- mtdcr(plb3_acr, addr | 0x80000000);
+ mfsdr(SD0_AMP1, addr);
+ mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
+ addr = mfdcr(PLB3_ACR);
+ mtdcr(PLB3_ACR, addr | 0x80000000);
/*
* Set priority for all PLB4 devices to 0.
*/
- mfsdr(sdr_amp0, addr);
- mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
- addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
- mtdcr(plb4_acr, addr);
+ mfsdr(SD0_AMP0, addr);
+ mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
+ addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
+ mtdcr(PLB4_ACR, addr);
/*
* Set Nebula PLB4 arbiter to fair mode.
*/
/* Segment0 */
- addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
- addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
- addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
- addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
- mtdcr(plb0_acr, addr);
+ addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
+ addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
+ addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
+ addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
+ mtdcr(PLB0_ACR, addr);
/* Segment1 */
- addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
- addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
- addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
- addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
- mtdcr(plb1_acr, addr);
+ addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
+ addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
+ addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
+ addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
+ mtdcr(PLB1_ACR, addr);
return 1;
}
}
U_BOOT_CMD(
dcf77, 1, 1, do_dcf77,
- "dcf77 - Check DCF77 receiver\n",
- NULL
- );
+ "Check DCF77 receiver",
+ ""
+);
/*
* initialize USB hub via I2C1
}
U_BOOT_CMD(
hubinit, 1, 1, do_hubinit,
- "hubinit - Initialize USB hub\n",
- NULL
- );
+ "Initialize USB hub",
+ ""
+);
#endif /* CONFIG_I2C_MULTI_BUS */
#define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3
}
U_BOOT_CMD(
sbe, 2, 0, do_setup_boot_eeprom,
- "sbe - setup boot eeprom\n",
- NULL
- );
+ "setup boot eeprom",
+ ""
+);
#if defined(CONFIG_SYS_EEPROM_WREN)
/*
}
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
- "eepwren - Enable / disable / query EEPROM write access\n",
- NULL);
+ "Enable / disable / query EEPROM write access",
+ ""
+);
#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
static int got_pldirq;
static int pld_interrupt(u32 arg)
{
int rc = -1; /* not for us */
- u8 status = in8(CONFIG_SYS_CPLD_BASE);
+ u8 status = in_8((void *)CONFIG_SYS_CPLD_BASE);
/* check for PLD interrupt */
if (status & PWR_INT_FLAG) {
/* reset this int */
- out8(CONFIG_SYS_CPLD_BASE, 0);
+ out_8((void *)CONFIG_SYS_CPLD_BASE, 0);
rc = 0;
got_pldirq = 1; /* trigger backend */
}
got_pldirq = 0;
/* clear any pending interrupt */
- out8(CONFIG_SYS_CPLD_BASE, 0);
+ out_8((void *)CONFIG_SYS_CPLD_BASE, 0);
irq_install_handler(CPLD_IRQ,
(interrupt_handler_t *)pld_interrupt, 0);
if (got_pldirq) {
printf("Got interrupt!\n");
printf("Power %sready!\n",
- in8(CONFIG_SYS_CPLD_BASE) & PWR_RDY ? "":"NOT ");
+ in_8((void *)CONFIG_SYS_CPLD_BASE) &
+ PWR_RDY ? "":"NOT ");
}
irq_free_handler(CPLD_IRQ);
}
U_BOOT_CMD(
wpi, 1, 1, do_waitpwrirq,
- "wpi - Wait for power change interrupt\n",
- NULL
- );
+ "Wait for power change interrupt",
+ ""
+);
/*
* initialize DVI panellink transmitter
}
U_BOOT_CMD(
dviinit, 1, 1, do_dviinit,
- "dviinit - Initialize DVI Panellink transmitter\n",
- NULL
- );
+ "Initialize DVI Panellink transmitter",
+ ""
+);
/*
* TODO: 'time' command might be useful for others as well.
}
U_BOOT_CMD(
time, CONFIG_SYS_MAXARGS, 1, do_time,
- "time - run command and output execution time\n",
- NULL
- );
+ "run command and output execution time",
+ ""
+);
extern void video_hw_rectfill (
unsigned int bpp, /* bytes per pixel */
}
U_BOOT_CMD(
gfxdemo, CONFIG_SYS_MAXARGS, 1, do_gfxdemo,
- "gfxdemo - demo\n",
- NULL
- );
+ "demo",
+ ""
+);