#include <asm/io.h>
#include <command.h>
#include <malloc.h>
+#include <sja1000.h>
-
-#if 0
-#define FPGA_DEBUG
-#endif
+#undef FPGA_DEBUG
DECLARE_GLOBAL_DATA_PTR;
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
extern void lxt971_no_sleep(void);
/* fpga configuration data - gzip compressed and generated by bin2c */
*/
#include "../common/fpga.c"
-
/*
- * include common auto-update code (for esd boards)
+ * generate a short spike on the CAN tx line
+ * to bring the couplers in sync
*/
-#include "../common/auto_update.h"
-
-au_image_t au_image[] = {
- {"plu405/preinst.img", 0, -1, AU_SCRIPT},
- {"plu405/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
- {"plu405/pImage_${bd_type}", 0x00000000, 0x00100000, AU_NAND},
- {"plu405/pImage.initrd", 0x00100000, 0x00200000, AU_NAND},
- {"plu405/yaffsmt2.img", 0x00300000, 0x01c00000, AU_NAND},
- {"plu405/postinst.img", 0, 0, AU_SCRIPT},
-};
-
-int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
-
-/* Prototypes */
-int gunzip(void *, int, unsigned char *, unsigned long *);
+void init_coupler(u32 addr)
+{
+ struct sja1000_basic_s *ctrl = (struct sja1000_basic_s *)addr;
+
+ /* reset */
+ out_8(&ctrl->cr, CR_RR);
+
+ /* dominant */
+ out_8(&ctrl->btr0, 0x00); /* btr setup is required */
+ out_8(&ctrl->btr1, 0x14); /* we use 1Mbit/s */
+ out_8(&ctrl->oc, OC_TP1 | OC_TN1 | OC_POL1 |
+ OC_TP0 | OC_TN0 | OC_POL0 | OC_MODE1);
+ out_8(&ctrl->cr, 0x00);
+
+ /* delay */
+ in_8(&ctrl->cr);
+ in_8(&ctrl->cr);
+ in_8(&ctrl->cr);
+ in_8(&ctrl->cr);
+
+ /* reset */
+ out_8(&ctrl->cr, CR_RR);
+}
-int board_early_init_f (void)
+int board_early_init_f(void)
{
/*
* IRQ 0-15 405GP internally generated; active high; level sensitive
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
- mtdcr(uicer, 0x00000000); /* disable all ints */
- mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
- mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
- mtdcr(uictr, 0x10000000); /* set int trigger levels */
- mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest prio */
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
+ mtdcr(UIC0PR, 0xFFFFFF99); /* set int polarities */
+ mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to
* 512 ebc-clks -> ca. 15 us
*/
- mtebc (epcr, 0xa8400000); /* ebc always driven */
+ mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
return 0;
}
-int misc_init_r (void)
+int misc_init_r(void)
{
- unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
- unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
unsigned char *dst;
unsigned char fctr;
ulong len = sizeof(fpgadata);
gd->bd->bi_flashoffset = 0;
dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
- if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
- printf ("GUNZIP ERROR - must RESET board to recover\n");
- do_reset (NULL, 0, 0, NULL);
+ if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
+ (uchar *)fpgadata, &len) != 0) {
+ printf("GUNZIP ERROR - must RESET board to recover\n");
+ do_reset(NULL, 0, 0, NULL);
}
status = fpga_boot(dst, len);
for (index=0;index<1000;index++)
udelay(1000);
}
- putc ('\n');
+ putc('\n');
do_reset(NULL, 0, 0, NULL);
}
printf("%s ", &(dst[index+1]));
index += len+3;
}
- putc ('\n');
+ putc('\n');
free(dst);
/*
* Reset external DUARTs
*/
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST);
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST);
udelay(10);
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
udelay(1000);
/*
* Set NAND-FLASH GPIO signals to default
*/
out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE);
+ in_be32((void*)GPIO0_OR) &
+ ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE);
/*
* Setup EEPROM write protection
*/
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
- out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP);
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+ out_be32((void*)GPIO0_TCR,
+ in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP);
/*
* Enable interrupts in exar duart mcr[3]
*/
- out_8(duart0_mcr, 0x08);
- out_8(duart1_mcr, 0x08);
+ out_8((void *)DUART0_BA + 4, 0x08);
+ out_8((void *)DUART1_BA + 4, 0x08);
/*
* Enable auto RS485 mode in 2nd external uart
out_8((void *)DUART1_BA + 1, fctr); /* write FCTR */
out_8((void *)DUART1_BA + 3, 0); /* write LCR */
- return (0);
+ /*
+ * Init magnetic couplers
+ */
+ if (!getenv("noinitcoupler")) {
+ init_coupler(CAN0_BA);
+ init_coupler(CAN1_BA);
+ }
+ return 0;
}
/*
* Check Board Identity:
*/
-int checkboard (void)
+int checkboard(void)
{
char str[64];
- int i = getenv_r ("serial#", str, sizeof(str));
+ int i = getenv_f("serial#", str, sizeof(str));
- puts ("Board: ");
+ puts("Board: ");
- if (i == -1) {
- puts ("### No HW ID - assuming PLU405");
- } else {
+ if (i == -1)
+ puts("### No HW ID - assuming PLU405");
+ else
puts(str);
- }
- putc ('\n');
+ putc('\n');
return 0;
}
#ifdef CONFIG_IDE_RESET
+#define FPGA_CTRL (CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL)
void ide_set_reset(int on)
{
- volatile unsigned short *fpga_mode =
- (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
-
/*
* Assert or deassert CompactFlash Reset Pin
*/
if (on) { /* assert RESET */
- *fpga_mode &= ~(CONFIG_SYS_FPGA_CTRL_CF_RESET);
+ out_be16((void *)FPGA_CTRL,
+ in_be16((void *)FPGA_CTRL) &
+ ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
} else { /* release RESET */
- *fpga_mode |= CONFIG_SYS_FPGA_CTRL_CF_RESET;
+ out_be16((void *)FPGA_CTRL,
+ in_be16((void *)FPGA_CTRL) |
+ CONFIG_SYS_FPGA_CTRL_CF_RESET);
}
}
#endif /* CONFIG_IDE_RESET */
#if defined(CONFIG_SYS_EEPROM_WREN)
/* Input: <dev_addr> I2C address of EEPROM device to enable.
- * <state> -1: deliver current state
- * 0: disable write
- * 1: enable write
- * Returns: -1: wrong device address
- * 0: dis-/en- able done
- * 0/1: current state if <state> was -1.
+ * <state> -1: deliver current state
+ * 0: disable write
+ * 1: enable write
+ * Returns: -1: wrong device address
+ * 0: dis-/en- able done
+ * 0/1: current state if <state> was -1.
*/
-int eeprom_write_enable (unsigned dev_addr, int state)
+int eeprom_write_enable(unsigned dev_addr, int state)
{
if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
return -1;
case 1:
/* Enable write access, clear bit GPIO0. */
out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
+ in_be32((void*)GPIO0_OR) &
+ ~CONFIG_SYS_EEPROM_WP);
state = 0;
break;
case 0:
/* Disable write access, set bit GPIO0. */
out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+ in_be32((void*)GPIO0_OR) |
+ CONFIG_SYS_EEPROM_WP);
state = 0;
break;
default:
/* Read current status back. */
- state = (0 == (in_be32((void*)GPIO0_OR) &
- CONFIG_SYS_EEPROM_WP));
+ state = ((in_be32((void*)GPIO0_OR) &
+ CONFIG_SYS_EEPROM_WP) == 0);
break;
}
}
return state;
}
-int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int query = argc == 1;
int state = 0;
if (query) {
/* Query write access state. */
- state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
+ state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
if (state < 0) {
- puts ("Query of write access state failed.\n");
+ puts("Query of write access state failed.\n");
} else {
- printf ("Write access for device 0x%0x is %sabled.\n",
- CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
+ printf("Write access for device 0x%0x is %sabled.\n",
+ CONFIG_SYS_I2C_EEPROM_ADDR,
+ state ? "en" : "dis");
state = 0;
}
} else {
- if ('0' == argv[1][0]) {
+ if (argv[1][0] == '0') {
/* Disable write access. */
- state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
+ state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
+ 0);
} else {
/* Enable write access. */
- state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
- }
- if (state < 0) {
- puts ("Setup of write access state failed.\n");
+ state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
+ 1);
}
+ if (state < 0)
+ puts("Setup of write access state failed.\n");
}
return state;
}
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
- "Enable / disable / query EEPROM write access",
- NULL);
+ "Enable / disable / query EEPROM write access",
+ ""
+);
#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */