]> git.sur5r.net Git - u-boot/blobdiff - board/esd/plu405/plu405.c
Merge branch 'master' of git://git.denx.de/u-boot-ubi
[u-boot] / board / esd / plu405 / plu405.c
index e41545a9369c8badbf3b2d17c91ecb9861a4a276..f14ef7a20f843a88ff0f48e34ae22f2b11301a0e 100644 (file)
@@ -78,19 +78,19 @@ int board_early_init_f(void)
         * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
         * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
         */
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-       mtdcr(uicer, 0x00000000);       /* disable all ints */
-       mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-       mtdcr(uicpr, 0xFFFFFF99);       /* set int polarities */
-       mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-       mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest prio */
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+       mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+       mtdcr(UIC0PR, 0xFFFFFF99);       /* set int polarities */
+       mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+       mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest prio */
+       mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 
        /*
         * EBC Configuration Register: set ready timeout to
         * 512 ebc-clks -> ca. 15 us
         */
-       mtebc(epcr, 0xa8400000); /* ebc always driven */
+       mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
 
        return 0;
 }