Merge branch 'next' of ../master

[u-boot] / board / esd / plu405 / plu405.c

diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c
index 3db9c0ad100d5d3a79e25764c213087090ac0c6a..fdacbf6f6b121be933bae800e2e1760be1be040a 100644 (file)
--- a/board/esd/plu405/plu405.c
+++ b/board/esd/plu405/plu405.c
@@ -104,6 +104,7 @@ int misc_init_r (void)
        unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
        unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
        unsigned char *dst;
+       unsigned char fctr;
        ulong len = sizeof(fpgadata);
        int status;
        int index;
@@ -113,8 +114,8 @@ int misc_init_r (void)
        gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
        gd->bd->bi_flashoffset = 0;
 
-       dst = malloc(CFG_FPGA_MAX_SIZE);
-       if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+       dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+       if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
                printf ("GUNZIP ERROR - must RESET board to recover\n");
                do_reset (NULL, 0, 0, NULL);
        }
@@ -179,23 +180,23 @@ int misc_init_r (void)
        /*
         * Reset external DUARTs
         */
-       out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_DUART_RST);
+       out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST);
        udelay(10);
-       out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_DUART_RST);
+       out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
        udelay(1000);
 
        /*
         * Set NAND-FLASH GPIO signals to default
         */
        out_be32((void*)GPIO0_OR,
-                in_be32((void*)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
-       out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_NAND_CE);
+                in_be32((void*)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
+       out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE);
 
        /*
         * Setup EEPROM write protection
         */
-       out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
-       out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_EEPROM_WP);
+       out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+       out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP);
 
        /*
         * Enable interrupts in exar duart mcr[3]
@@ -203,6 +204,15 @@ int misc_init_r (void)
        out_8(duart0_mcr, 0x08);
        out_8(duart1_mcr, 0x08);
 
+       /*
+        * Enable auto RS485 mode in 2nd external uart
+        */
+       out_8((void *)DUART1_BA + 3, 0xbf); /* write LCR */
+       fctr = in_8((void *)DUART1_BA + 1); /* read FCTR */
+       fctr |= 0x08;                       /* enable RS485 mode */
+       out_8((void *)DUART1_BA + 1, fctr); /* write FCTR */
+       out_8((void *)DUART1_BA + 3, 0);    /* write LCR */
+
        return (0);
 }
 
@@ -227,18 +237,18 @@ int checkboard (void)
 }
 
 #ifdef CONFIG_IDE_RESET
+#define FPGA_CTRL (CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL)
 void ide_set_reset(int on)
 {
-       volatile unsigned short *fpga_mode =
-               (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
-
        /*
         * Assert or deassert CompactFlash Reset Pin
         */
        if (on) {               /* assert RESET */
-               *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
+               out_be16((void *)FPGA_CTRL,
+                        in_be16((void *)FPGA_CTRL) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
        } else {                /* release RESET */
-               *fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
+               out_be16((void *)FPGA_CTRL,
+                        in_be16((void *)FPGA_CTRL) | CONFIG_SYS_FPGA_CTRL_CF_RESET);
        }
 }
 #endif /* CONFIG_IDE_RESET */
@@ -254,7 +264,7 @@ void reset_phy(void)
 #endif
 }
 
-#if defined(CFG_EEPROM_WREN)
+#if defined(CONFIG_SYS_EEPROM_WREN)
 /* Input: <dev_addr>  I2C address of EEPROM device to enable.
  *         <state>     -1: deliver current state
  *                    0: disable write
@@ -265,26 +275,26 @@ void reset_phy(void)
  */
 int eeprom_write_enable (unsigned dev_addr, int state)
 {
-       if (CFG_I2C_EEPROM_ADDR != dev_addr) {
+       if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
                return -1;
        } else {
                switch (state) {
                case 1:
                        /* Enable write access, clear bit GPIO0. */
                        out_be32((void*)GPIO0_OR,
-                                in_be32((void*)GPIO0_OR) & ~CFG_EEPROM_WP);
+                                in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
                        state = 0;
                        break;
                case 0:
                        /* Disable write access, set bit GPIO0. */
                        out_be32((void*)GPIO0_OR,
-                                in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
+                                in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
                        state = 0;
                        break;
                default:
                        /* Read current status back. */
                        state = (0 == (in_be32((void*)GPIO0_OR) &
-                                      CFG_EEPROM_WP));
+                                      CONFIG_SYS_EEPROM_WP));
                        break;
                }
        }
@@ -298,21 +308,21 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
        if (query) {
                /* Query write access state. */
-               state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
+               state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
                if (state < 0) {
                        puts ("Query of write access state failed.\n");
                } else {
                        printf ("Write access for device 0x%0x is %sabled.\n",
-                               CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
+                               CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
                        state = 0;
                }
        } else {
                if ('0' == argv[1][0]) {
                        /* Disable write access. */
-                       state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
+                       state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
                } else {
                        /* Enable write access. */
-                       state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
+                       state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
                }
                if (state < 0) {
                        puts ("Setup of write access state failed.\n");
@@ -323,6 +333,7 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 }
 
 U_BOOT_CMD(eepwren,    2,      0,      do_eep_wren,
-          "eepwren - Enable / disable / query EEPROM write access\n",
-          NULL);
-#endif /* #if defined(CFG_EEPROM_WREN) */
+       "Enable / disable / query EEPROM write access",
+       ""
+);
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */