unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
unsigned char *dst;
+ unsigned char fctr;
ulong len = sizeof(fpgadata);
int status;
int index;
out_8(duart0_mcr, 0x08);
out_8(duart1_mcr, 0x08);
+ /*
+ * Enable auto RS485 mode in 2nd external uart
+ */
+ out_8((void *)DUART1_BA + 3, 0xbf); /* write LCR */
+ fctr = in_8((void *)DUART1_BA + 1); /* read FCTR */
+ fctr |= 0x08; /* enable RS485 mode */
+ out_8((void *)DUART1_BA + 1, fctr); /* write FCTR */
+ out_8((void *)DUART1_BA + 3, 0); /* write LCR */
+
return (0);
}
}
#ifdef CONFIG_IDE_RESET
+#define FPGA_CTRL (CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL)
void ide_set_reset(int on)
{
- volatile unsigned short *fpga_mode =
- (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
-
/*
* Assert or deassert CompactFlash Reset Pin
*/
if (on) { /* assert RESET */
- *fpga_mode &= ~(CONFIG_SYS_FPGA_CTRL_CF_RESET);
+ out_be16((void *)FPGA_CTRL,
+ in_be16((void *)FPGA_CTRL) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
} else { /* release RESET */
- *fpga_mode |= CONFIG_SYS_FPGA_CTRL_CF_RESET;
+ out_be16((void *)FPGA_CTRL,
+ in_be16((void *)FPGA_CTRL) | CONFIG_SYS_FPGA_CTRL_CF_RESET);
}
}
#endif /* CONFIG_IDE_RESET */
}
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
- "eepwren - Enable / disable / query EEPROM write access\n",
- NULL);
+ "Enable / disable / query EEPROM write access",
+ ""
+);
#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */