Merge branch 'master' of git://git.denx.de/u-boot-fdt

[u-boot] / board / esd / pmc405 / pmc405.c

diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c
index dd58d0124ea641f820613d032f2f9b1253a2a114..03143fe487b83bf8bf5e8ce011749f477cefa4f9 100644 (file)
--- a/board/esd/pmc405/pmc405.c
+++ b/board/esd/pmc405/pmc405.c
@@ -2,7 +2,7 @@
  * (C) Copyright 2001-2003
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
- * (C) Copyright 2005
+ * (C) Copyright 2005-2009
  * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
  *
  * See file CREDITS for list of people who contributed to this
@@ -26,6 +26,7 @@
 
 #include <common.h>
 #include <asm/processor.h>
+#include <asm/io.h>
 #include <command.h>
 #include <malloc.h>
 
@@ -33,13 +34,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 extern void lxt971_no_sleep(void);
 
-/* fpga configuration data - not compressed, generated by bin2c */
-const unsigned char fpgadata[] =
-{
-#include "fpgadata.c"
-};
-int filesize = sizeof(fpgadata);
-
 int board_early_init_f (void)
 {
        /*
@@ -54,39 +48,39 @@ int board_early_init_f (void)
         * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
         * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
         */
-       mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
-       mtdcr(uicer, 0x00000000); /* disable all ints */
-       mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
-       mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
-       mtdcr(uictr, 0x10000000); /* set int trigger levels */
-       mtdcr(uicvcr, 0x00000001); /* set vect base=0, INT0 highest priority */
-       mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+       mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+       mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+       mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
+       mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
+       mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
+       mtdcr(UIC0VCR, 0x00000001); /* set vect base=0, INT0 highest priority */
+       mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
 
        /*
         * EBC Configuration Register:
         * set ready timeout to 512 ebc-clks -> ca. 15 us
         */
-       mtebc (epcr, 0xa8400000);
+       mtebc (EBC0_CFG, 0xa8400000);
 
        /*
         * Setup GPIO pins
         */
-       mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_FPGA_INIT | \
-                                       CONFIG_SYS_FPGA_DONE | \
-                                       CONFIG_SYS_XEREADY | \
-                                       CONFIG_SYS_NONMONARCH | \
+       mtdcr(CPC0_CR0, mfdcr(CPC0_CR0) | ((CONFIG_SYS_FPGA_INIT |
+                                       CONFIG_SYS_FPGA_DONE |
+                                       CONFIG_SYS_XEREADY |
+                                       CONFIG_SYS_NONMONARCH |
                                        CONFIG_SYS_REV1_2) << 5));
 
-       if (!(in32(GPIO0_IR) & CONFIG_SYS_REV1_2)) {
+       if (!(in_be32((void *)GPIO0_IR) & CONFIG_SYS_REV1_2)) {
                /* rev 1.2 boards */
-               mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_INTA_FAKE | \
+               mtdcr(CPC0_CR0, mfdcr(CPC0_CR0) | ((CONFIG_SYS_INTA_FAKE |
                                                CONFIG_SYS_SELF_RST) << 5));
        }
 
-       out32(GPIO0_OR, 0);
+       out_be32((void *)GPIO0_OR, CONFIG_SYS_VPEN);
        /* setup for output */
-       out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK | \
-             CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY);
+       out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK |
+                CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY | CONFIG_SYS_VPEN);
 
        /*
         * - check if rev1_2 is low, then:
@@ -103,14 +97,16 @@ int misc_init_r (void)
        gd->bd->bi_flashoffset = 0;
 
        /* deassert EREADY# */
-       out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_XEREADY);
+       out_be32((void *)GPIO0_OR,
+                in_be32((void *)GPIO0_OR) | CONFIG_SYS_XEREADY);
        return (0);
 }
 
 ushort pmc405_pci_subsys_deviceid(void)
 {
        ulong val;
-       val = in32(GPIO0_IR);
+
+       val = in_be32((void *)GPIO0_IR);
        if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */
                /* check monarch# signal */
                if (val & CONFIG_SYS_NONMONARCH)
@@ -126,9 +122,8 @@ ushort pmc405_pci_subsys_deviceid(void)
 int checkboard (void)
 {
        ulong val;
-
        char str[64];
-       int i = getenv_r ("serial#", str, sizeof(str));
+       int i = getenv_f("serial#", str, sizeof(str));
 
        puts ("Board: ");
 
@@ -137,7 +132,7 @@ int checkboard (void)
        else
                puts(str);
 
-       val = in32(GPIO0_IR);
+       val = in_be32((void *)GPIO0_IR);
        if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */
                puts(" rev1.2 (");
                if (val & CONFIG_SYS_NONMONARCH) /* monarch# signal */