Replace CONFIG_SYS_GBL_DATA_SIZE by auto-generated value

[u-boot] / board / esd / pmc440 / init.S

diff --git a/board/esd/pmc440/init.S b/board/esd/pmc440/init.S
index 6585fed664746243d67e43501fa850f9511d1b49..b99a8e9792bfb2e8b4e9835db9a15e27645b0e56 100644 (file)
--- a/board/esd/pmc440/init.S
+++ b/board/esd/pmc440/init.S
@@ -19,8 +19,9 @@
  * MA 02111-1307 USA
  */
 
+#include <asm-offsets.h>
 #include <ppc_asm.tmpl>
-#include <asm-ppc/mmu.h>
+#include <asm/mmu.h>
 #include <config.h>
 
 /*
@@ -44,23 +45,23 @@ tlbtab:
         * speed up boot process. It is patched after relocation to enable SA_I
         */
 #ifndef CONFIG_NAND_SPL
-       tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
+       tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
 #else
-       tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G )
+       tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G )
 #endif
 
        /* TLB entries for DDR2 SDRAM are generated dynamically */
 
 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
        /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-       tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+       tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
 #endif
 
        /* TLB-entry for PCI Memory */
-       tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
-       tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
+       tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG )
+       tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG )
+       tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG )
+       tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG )
 
        /* TLB-entries for EBC */
        /* PMC440 maps EBC to 0xef000000 which is handled by the peripheral
@@ -68,22 +69,22 @@ tlbtab:
         * This dummy entry is only for convinience in order not to modify the
         * amount of entries. Currently OS/9 relies on this :-)
         */
-       tlbentry( 0xc0000000, SZ_256M, 0xc0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+       tlbentry( 0xc0000000, SZ_256M, 0xc0000000, 1, AC_RWX | SA_IG )
 
        /* TLB-entry for NAND */
-       tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+       tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_RWX | SA_IG )
 
        /* TLB-entry for Internal Registers & OCM */
-       tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,  AC_R|AC_W|AC_X|SA_I )
+       tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,  AC_RWX | SA_I )
 
        /*TLB-entry PCI registers*/
-       tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1,  AC_R|AC_W|AC_X|SA_G|SA_I )
+       tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1,  AC_RWX | SA_IG )
 
        /* TLB-entry for peripherals */
-       tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+       tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
 
        /* TLB-entry PCI IO space */
-       tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+       tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG)
 
        /* TODO:  what about high IO space */
        tlbtab_end
@@ -95,7 +96,7 @@ tlbtab:
         */
 #define TLB00  TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
 #define TLB01  TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
-#define TLB02  TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
+#define TLB02  TLB2(AC_RWX | SA_IG)
 
        .globl  reconfig_tlb0
 reconfig_tlb0: