Merge branch 'next' of git://git.denx.de/u-boot-mpc83xx

[u-boot] / board / esd / pmc440 / pmc440.h

diff --git a/board/esd/pmc440/pmc440.h b/board/esd/pmc440/pmc440.h
index d834f258571ccccd7a8500bb61605a925a675b68..84e0b1f46c466b0342edf3ae5c4a5a587e92a186 100644 (file)
--- a/board/esd/pmc440/pmc440.h
+++ b/board/esd/pmc440/pmc440.h
@@ -1,31 +1,14 @@
 /*
- * (C) Copyright 2007
+ * (C) Copyright 2007-2008
  * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __PMC440_H__
 #define __PMC440_H__
 
-
-/*-----------------------------------------------------------------------
+/*
  * GPIOs
  */
 #define GPIO1_INTA_FAKE           (0x80000000 >> (45-32)) /* GPIO45 OD */
@@ -41,9 +24,10 @@
 #define GPIO0_EP_EEP              (0x80000000 >> 23)      /* GPIO23 O */
 #define GPIO0_USB_ID              (0x80000000 >> 21)      /* GPIO21 I */
 #define GPIO0_USB_PRSNT           (0x80000000 >> 20)      /* GPIO20 I */
-#define GPIO0_SELF_RST            (0x80000000 >> 6)       /* GPIO6  OD */
 
-/* FPGA programming pin configuration */
+/*
+ * FPGA programming pin configuration
+ */
 #define GPIO1_FPGA_PRG            (0x80000000 >> (53-32)) /* FPGA program pin (ppc output) */
 #define GPIO1_FPGA_CLK            (0x80000000 >> (51-32)) /* FPGA clk pin (ppc output)     */
 #define GPIO1_FPGA_DATA           (0x80000000 >> (52-32)) /* FPGA data pin (ppc output)    */
@@ -51,7 +35,7 @@
 #define GPIO1_FPGA_INIT           (0x80000000 >> (54-32)) /* FPGA init pin (ppc input)     */
 #define GPIO0_FPGA_FORCEINIT      (0x80000000 >> 27)      /* low: force INIT# low */
 
-/*-----------------------------------------------------------------------
+/*
  * FPGA interface
  */
 #define FPGA_BA CONFIG_SYS_FPGA_BASE0
@@ -103,7 +87,6 @@ typedef struct pmc440_fpga_s pmc440_fpga_t;
 #define RESET_OUT   (1 << 19)
 #define IRIGB_R_OUT (1 << 14)
 
-
 /* status register */
 #define STATUS_VERSION_SHIFT 24
 #define STATUS_VERSION_MASK  0xff000000
@@ -115,13 +98,11 @@ typedef struct pmc440_fpga_s pmc440_fpga_t;
 #define STATUS_FIFO_ISF      (1 <<  9)
 #define STATUS_HOST_ISF      (1 <<  8)
 
-
 /* inputs */
 #define RESET_IN    (1 << 0)
 #define CLOCK_IN    (1 << 1)
 #define IRIGB_R_IN  (1 << 5)
 
-
 /* hostctrl register */
 #define HOSTCTRL_PMCRSTOUT_GATE (1 <<  17)
 #define HOSTCTRL_PMCRSTOUT_FLAG (1 <<  16)
@@ -137,7 +118,7 @@ typedef struct pmc440_fpga_s pmc440_fpga_t;
 #define NGCC_CTRL_BASE         (CONFIG_SYS_FPGA_BASE0 + 0x80000)
 #define NGCC_CTRL_FPGARST_N    (1 <<  2)
 
-/*-----------------------------------------------------------------------
+/*
  * FPGA to PPC interrupt
  */
 #define IRQ0_FPGA            (32+28) /* UIC1 - FPGA internal */