/*
- * (C) Copyright 2001-2003
+ * (C) Copyright 2001-2004
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
*/
#include <common.h>
+#include <asm/io.h>
#include <asm/processor.h>
#include <command.h>
#include <malloc.h>
#endif
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+extern void lxt971_no_sleep(void);
/* fpga configuration data - gzip compressed and generated by bin2c */
const unsigned char fpgadata[] =
/* Prototypes */
-int gunzip(void *, int, unsigned char *, int *);
+int gunzip(void *, int, unsigned char *, unsigned long *);
+
+
+/* logo bitmap data - gzip compressed and generated by bin2c */
+unsigned char logo_bmp_320[] =
+{
+#include "logo_320_240_4bpp.c"
+};
+
+unsigned char logo_bmp_640[] =
+{
+#include "logo_640_480_24bpp.c"
+};
+
+
+/*
+ * include common lcd code (for esd boards)
+ */
+#include "../common/lcd.c"
+
+#include "../common/s1d13704_320_240_4bpp.h"
+#include "../common/s1d13806_320_240_4bpp.h"
+#include "../common/s1d13806_640_480_16bpp.h"
int board_early_init_f (void)
}
-/* ------------------------------------------------------------------------- */
-
int misc_init_f (void)
{
return 0; /* dummy implementation */
int misc_init_r (void)
{
- volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
- volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
- volatile unsigned short *lcd_reg =
+ unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
+ unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
+ unsigned short *lcd_contrast =
(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 4);
+ unsigned short *lcd_backlight =
+ (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 6);
unsigned char *dst;
ulong len = sizeof(fpgadata);
int status;
int index;
int i;
+ char *str;
dst = malloc(CFG_FPGA_MAX_SIZE);
- if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
+ if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
printf ("GUNZIP ERROR - must RESET board to recover\n");
do_reset (NULL, 0, 0, NULL);
}
free(dst);
/*
- * Reset FPGA via FPGA_DATA pin
+ * Reset FPGA via FPGA_INIT pin
*/
- SET_FPGA(FPGA_PRG | FPGA_CLK);
+ out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~FPGA_INIT); /* reset low */
udelay(1000); /* wait 1ms */
- SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | FPGA_INIT); /* reset high */
udelay(1000); /* wait 1ms */
/*
* Reset external DUARTs
*/
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
udelay(10); /* wait 10us */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
udelay(1000); /* wait 1ms */
/*
* Set NAND-FLASH GPIO signals to default
*/
- out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_NAND_CE);
+
+ /*
+ * Setup EEPROM write protection
+ */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
+ out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_EEPROM_WP);
/*
* Enable interrupts in exar duart mcr[3]
*/
- *duart0_mcr = 0x08;
- *duart1_mcr = 0x08;
+ out_8(duart0_mcr, 0x08);
+ out_8(duart1_mcr, 0x08);
+
+ /*
+ * Init lcd interface and display logo
+ */
+ str = getenv("bd_type");
+ if (strcmp(str, "voh405_bw") == 0) {
+ lcd_setup(0, 1);
+ lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
+ regs_13704_320_240_4bpp,
+ sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
+ logo_bmp_320, sizeof(logo_bmp_320));
+ } else if (strcmp(str, "voh405_bwbw") == 0) {
+ lcd_setup(0, 1);
+ lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
+ regs_13704_320_240_4bpp,
+ sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
+ logo_bmp_320, sizeof(logo_bmp_320));
+ lcd_setup(1, 1);
+ lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
+ regs_13806_320_240_4bpp,
+ sizeof(regs_13806_320_240_4bpp)/sizeof(regs_13806_320_240_4bpp[0]),
+ logo_bmp_320, sizeof(logo_bmp_320));
+ } else if (strcmp(str, "voh405_bwc") == 0) {
+ lcd_setup(0, 1);
+ lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
+ regs_13704_320_240_4bpp,
+ sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
+ logo_bmp_320, sizeof(logo_bmp_320));
+ lcd_setup(1, 0);
+ lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
+ regs_13806_640_480_16bpp,
+ sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
+ logo_bmp_640, sizeof(logo_bmp_640));
+ } else {
+ printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
+ return 0;
+ }
+
+ /*
+ * Set invert bit in small lcd controller
+ */
+ out_8((unsigned char *)(CFG_LCD_SMALL_REG + 2),
+ in_8((unsigned char *)(CFG_LCD_SMALL_REG + 2)) | 0x01);
/*
* Set default contrast voltage on epson vga controller
*/
- *lcd_reg = 0x4848;
+ out_be16(lcd_contrast, 0x4646);
+
+ /*
+ * Enable backlight
+ */
+ out_be16(lcd_backlight, 0xffff);
+
+ /*
+ * Enable external I2C bus
+ */
+ out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_IIC_ON);
return (0);
}
int checkboard (void)
{
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
puts ("Board: ");
puts(str);
}
+ if (getenv_r("bd_type", str, sizeof(str)) != -1) {
+ printf(" (%s)", str);
+ } else {
+ puts(" (Missing bd_type!)");
+ }
+
putc ('\n');
return 0;
}
#endif /* CONFIG_IDE_RESET */
+#if defined(CONFIG_RESET_PHY_R)
+void reset_phy(void)
+{
+#ifdef CONFIG_LXT971_NO_SLEEP
+
+ /*
+ * Disable sleep mode in LXT971
+ */
+ lxt971_no_sleep();
+#endif
+}
+#endif
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
-#include <linux/mtd/nand.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+#if defined(CFG_EEPROM_WREN)
+/* Input: <dev_addr> I2C address of EEPROM device to enable.
+ * <state> -1: deliver current state
+ * 0: disable write
+ * 1: enable write
+ * Returns: -1: wrong device address
+ * 0: dis-/en- able done
+ * 0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable (unsigned dev_addr, int state)
+{
+ if (CFG_I2C_EEPROM_ADDR != dev_addr) {
+ return -1;
+ } else {
+ switch (state) {
+ case 1:
+ /* Enable write access, clear bit GPIO0. */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_EEPROM_WP);
+ state = 0;
+ break;
+ case 0:
+ /* Disable write access, set bit GPIO0. */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
+ state = 0;
+ break;
+ default:
+ /* Read current status back. */
+ state = (0 == (in_be32((void*)GPIO0_OR) & CFG_EEPROM_WP));
+ break;
+ }
+ }
+ return state;
+}
-void nand_init(void)
+int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
- nand_probe(CFG_NAND_BASE);
- if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
- print_size(nand_dev_desc[0].totlen, "\n");
+ int query = argc == 1;
+ int state = 0;
+
+ if (query) {
+ /* Query write access state. */
+ state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
+ if (state < 0) {
+ puts ("Query of write access state failed.\n");
+ } else {
+ printf ("Write access for device 0x%0x is %sabled.\n",
+ CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
+ state = 0;
+ }
+ } else {
+ if ('0' == argv[1][0]) {
+ /* Disable write access. */
+ state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
+ } else {
+ /* Enable write access. */
+ state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
+ }
+ if (state < 0) {
+ puts ("Setup of write access state failed.\n");
+ }
}
+
+ return state;
}
-#endif
+
+U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
+ "eepwren - Enable / disable / query EEPROM write access\n",
+ NULL);
+#endif /* #if defined(CFG_EEPROM_WREN) */
projects / u-boot / blobdiff