Merge 'next' branch

[u-boot] / board / evb64260 / eth.c

diff --git a/board/evb64260/eth.c b/board/evb64260/eth.c
index 8b3a35923863149aa87fd185eba1df39923caa94..ca8bab52d96613c9d416a9d0f6ac36d9596629e1 100644 (file)
--- a/board/evb64260/eth.c
+++ b/board/evb64260/eth.c
@@ -22,17 +22,17 @@ Skeleton NIC driver for Etherboot
 
 #include <common.h>
 #include <malloc.h>
-#include <cmd_bsp.h>
 #include <galileo/gt64260R.h>
 #include <galileo/core.h>
 #include <asm/cache.h>
 #include <miiphy.h>
 #include <net.h>
+#include <netdev.h>
 
 #include "eth.h"
 #include "eth_addrtbl.h"
 
-#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
 
 #define GT6426x_ETH_BUF_SIZE   1536
 
@@ -86,12 +86,17 @@ static const char ether_port_phy_addr[3]={0,1,2};
 static const char ether_port_phy_addr[3]={4,5,6};
 #endif
 
+/* MII PHY access routines are common for all i/f, use gal_ent0 */
+#define GT6426x_MII_DEVNAME    "gal_enet0"
+
+int gt6426x_miiphy_read(char *devname, unsigned char phy,
+               unsigned char reg, unsigned short *val);
 
 static inline unsigned short
 miiphy_read_ret(unsigned short phy, unsigned short reg)
 {
     unsigned short val;
-    miiphy_read(phy,reg,&val);
+    gt6426x_miiphy_read(GT6426x_MII_DEVNAME,phy,reg,&val);
     return val;
 }
 
@@ -159,7 +164,7 @@ gt6426x_eth_receive(struct eth_dev_s *p,unsigned int icr)
        int eth_len=0;
        char *eth_data;
 
-       eth0_rx_desc_single *rx=&p->eth_rx_desc[(p->rdn)];
+       eth0_rx_desc_single *rx = &p->eth_rx_desc[(p->rdn)];
 
        INVALIDATE_DCACHE((unsigned int)rx,(unsigned int)(rx+1));
 
@@ -183,7 +188,7 @@ gt6426x_eth_receive(struct eth_dev_s *p,unsigned int icr)
         */
 
        /* let the upper layer handle the packet */
-       NetReceive (eth_data, eth_len);
+       NetReceive ((uchar *)eth_data, eth_len);
 
        rx->buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16;
 
@@ -248,7 +253,7 @@ gt6426x_eth_transmit(void *v, volatile char *p, unsigned int s)
 #ifdef DEBUG
        unsigned int old_command_stat,old_psr;
 #endif
-       eth0_tx_desc_single *tx=&dev->eth_tx_desc[dev->tdn];
+       eth0_tx_desc_single *tx = &dev->eth_tx_desc[dev->tdn];
 
        /* wait for tx to be ready */
        INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1));
@@ -267,7 +272,7 @@ gt6426x_eth_transmit(void *v, volatile char *p, unsigned int s)
 #endif
        memcpy(dev->eth_tx_buffer, (char *) p, s);
 
-       tx->buff_pointer = dev->eth_tx_buffer;
+       tx->buff_pointer = (uchar *)dev->eth_tx_buffer;
        tx->bytecount_reserved = ((__u16)s) << 16;
 
        /*    31 - own
@@ -340,8 +345,8 @@ gt6426x_eth_disable(void *v)
 MII utilities - write: write to an MII register via SMI
 ***************************************************************************/
 int
-miiphy_write(unsigned char phy, unsigned char reg,
-    unsigned short data)
+gt6426x_miiphy_write(char *devname, unsigned char phy,
+               unsigned char reg, unsigned short data)
 {
     unsigned int temp= (reg<<21) | (phy<<16) | data;
 
@@ -355,8 +360,8 @@ miiphy_write(unsigned char phy, unsigned char reg,
 MII utilities - read: read from an MII register via SMI
 ***************************************************************************/
 int
-miiphy_read(unsigned char phy, unsigned char reg,
-                       unsigned short *val)
+gt6426x_miiphy_read(char *devname, unsigned char phy,
+               unsigned char reg, unsigned short *val)
 {
     unsigned int temp= (reg<<21) | (phy<<16) | 1<<26;
 
@@ -445,7 +450,7 @@ check_phy_state(struct eth_dev_s *p)
                if ((psr & 0x3) != want) {
                        printf("MII: GT thinks %x, PHY thinks %x, restarting autoneg..\n",
                                        psr & 0x3, want);
-                       miiphy_write(ether_port_phy_addr[p->dev],0,
+                       miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev],0,
                                        miiphy_read_ret(ether_port_phy_addr[p->dev],0) | (1<<9));
                        udelay(10000);  /* the EVB's GT takes a while to notice phy
                                           went down and up */
@@ -491,7 +496,7 @@ gt6426x_eth_probe(void *v, bd_t *bis)
           led 2: 0xc=link/rxact
           led 3: 0x2=rxact (N/C)
           strch: 0,2=30 ms, enable */
-       miiphy_write(ether_port_phy_addr[p->dev], 20, 0x1c22);
+       miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev], 20, 0x1c22);
 
        /* 2.7ns port rise time */
        /*miiphy_write(ether_port_phy_addr[p->dev], 30, 0x0<<10); */
@@ -525,7 +530,7 @@ gt6426x_eth_probe(void *v, bd_t *bis)
 #endif
 
        /* 31  28 27  24 23  20 19  16
-        *  0000   0000   0000   0000   [0004]
+        *  0000   0000   0000   0000   [0004]
         * 15  12 11  8   7  4   3  0
         *  1000   1101   0000   0000   [4d00]
         *    20 - 0=MII 1=RMII
@@ -584,7 +589,7 @@ gt6426x_eth_probe(void *v, bd_t *bis)
 
        /* Initialize Rx Side */
        for (temp = 0; temp < NR; temp++) {
-               p->eth_rx_desc[temp].buff_pointer = p->eth_rx_buffer[temp];
+               p->eth_rx_desc[temp].buff_pointer = (uchar *)p->eth_rx_buffer[temp];
                p->eth_rx_desc[temp].buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16;
 
                /* GT96100 Owner */
@@ -720,7 +725,8 @@ gt6426x_eth_initialize(bd_t *bis)
                dev->send = (void*)gt6426x_eth_transmit;
                dev->recv = (void*)gt6426x_eth_poll;
 
-               dev->priv = (void*)p = calloc( sizeof(*p), 1 );
+               p = calloc( sizeof(*p), 1 );
+               dev->priv = (void*)p;
                if (!p)
                {
                        printf( "%s: %s allocation failure, %s\n",
@@ -792,6 +798,11 @@ gt6426x_eth_initialize(bd_t *bis)
 
 
                eth_register(dev);
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+               miiphy_register(dev->name,
+                               gt6426x_miiphy_read, gt6426x_miiphy_write);
+#endif
        }
+
 }
-#endif /* CFG_CMD_NET && CONFIG_NET_MULTI */
+#endif