SPDX: Convert all of our single license tags to Linux Kernel style

[u-boot] / board / freescale / c29xpcie / ddr.c

diff --git a/board/freescale/c29xpcie/ddr.c b/board/freescale/c29xpcie/ddr.c
index b017cfd9613131fa9633dcaba78cdb53f34edc4f..5795a27f654fa6a5a1b22adf2638509acb3336c7 100644 (file)
--- a/board/freescale/c29xpcie/ddr.c
+++ b/board/freescale/c29xpcie/ddr.c
@@ -1,14 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
+#include <i2c.h>
 #include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 
+#include "cpld.h"
+
+#define C29XPCIE_HARDWARE_REVA 0x40
 /*
  * Micron MT41J128M16HA-15E
  * */
@@ -26,20 +29,20 @@ dimm_params_t ddr_raw_timing = {
        .edc_config = 2,
        .burst_lengths_bitmask = 0x0c,
 
-       .tCKmin_X_ps = 1650,
-       .caslat_X = 0x7e << 4,  /* 5,6,7,8,9,10 */
-       .tAA_ps = 14050,
-       .tWR_ps = 15000,
-       .tRCD_ps = 13500,
-       .tRRD_ps = 75000,
-       .tRP_ps = 13500,
-       .tRAS_ps = 40000,
-       .tRC_ps = 49500,
-       .tRFC_ps = 160000,
-       .tWTR_ps = 75000,
-       .tRTP_ps = 75000,
+       .tckmin_x_ps = 1650,
+       .caslat_x = 0x7e << 4,  /* 5,6,7,8,9,10 */
+       .taa_ps = 14050,
+       .twr_ps = 15000,
+       .trcd_ps = 13500,
+       .trrd_ps = 75000,
+       .trp_ps = 13500,
+       .tras_ps = 40000,
+       .trc_ps = 49500,
+       .trfc_ps = 160000,
+       .twtr_ps = 75000,
+       .trtp_ps = 75000,
        .refresh_rate_ps = 7800000,
-       .tFAW_ps = 30000,
+       .tfaw_ps = 30000,
 };
 
 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
@@ -61,8 +64,10 @@ void fsl_ddr_board_options(memctl_options_t *popts,
                                dimm_params_t *pdimm,
                                unsigned int ctrl_num)
 {
+       struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
        int i;
-       popts->clk_adjust = 2;
+
+       popts->clk_adjust = 4;
        popts->cpo_override = 0x1f;
        popts->write_data_delay = 4;
        popts->half_strength_driver_enable = 1;
@@ -79,8 +84,23 @@ void fsl_ddr_board_options(memctl_options_t *popts,
        popts->trwt_override = 1;
        popts->trwt = 0;
 
+       if (in_8(&cpld_data->hwver) == C29XPCIE_HARDWARE_REVA)
+               popts->ecc_mode = 0;
+
        for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
                popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
                popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
        }
 }
+
+void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
+{
+       int ret = i2c_read(i2c_address, 0, 2, (uint8_t *)spd,
+                               sizeof(generic_spd_eeprom_t));
+
+       if (ret) {
+               printf("DDR: failed to read SPD from address %u\n",
+                               i2c_address);
+               memset(spd, 0, sizeof(generic_spd_eeprom_t));
+       }
+}