PPC 85xx QEMU: Always assume 1 core

[u-boot] / board / freescale / c29xpcie / ddr.c

diff --git a/board/freescale/c29xpcie/ddr.c b/board/freescale/c29xpcie/ddr.c
index 804ea1916d8050e132e2a73cebe68f6b33f1f37e..7c915b036f35303ad2b2e0b49c3dc7f842c86691 100644 (file)
--- a/board/freescale/c29xpcie/ddr.c
+++ b/board/freescale/c29xpcie/ddr.c
@@ -5,10 +5,14 @@
  */
 
 #include <common.h>
+#include <i2c.h>
 #include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 
+#include "cpld.h"
+
+#define C29XPCIE_HARDWARE_REVA 0x40
 /*
  * Micron MT41J128M16HA-15E
  * */
@@ -61,7 +65,9 @@ void fsl_ddr_board_options(memctl_options_t *popts,
                                dimm_params_t *pdimm,
                                unsigned int ctrl_num)
 {
+       struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
        int i;
+
        popts->clk_adjust = 4;
        popts->cpo_override = 0x1f;
        popts->write_data_delay = 4;
@@ -79,8 +85,23 @@ void fsl_ddr_board_options(memctl_options_t *popts,
        popts->trwt_override = 1;
        popts->trwt = 0;
 
+       if (in_8(&cpld_data->hwver) == C29XPCIE_HARDWARE_REVA)
+               popts->ecc_mode = 0;
+
        for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
                popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
                popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
        }
 }
+
+void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
+{
+       int ret = i2c_read(i2c_address, 0, 2, (uint8_t *)spd,
+                               sizeof(generic_spd_eeprom_t));
+
+       if (ret) {
+               printf("DDR: failed to read SPD from address %u\n",
+                               i2c_address);
+               memset(spd, 0, sizeof(generic_spd_eeprom_t));
+       }
+}