PPC 85xx QEMU: Always assume 1 core

[u-boot] / board / freescale / c29xpcie / tlb.c

diff --git a/board/freescale/c29xpcie/tlb.c b/board/freescale/c29xpcie/tlb.c
index 84844ee0f5120aefeb7f58ac061daa2f6b774034..c5abed05049b8e7b790ff19bfcdf0be24f993d40 100644 (file)
--- a/board/freescale/c29xpcie/tlb.c
+++ b/board/freescale/c29xpcie/tlb.c
@@ -30,6 +30,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
                        MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 0, BOOKE_PAGESZ_1M, 1),
 
+#ifndef CONFIG_SPL_BUILD
        SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
                        MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
                        0, 1, BOOKE_PAGESZ_64M, 1),
@@ -42,6 +43,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
        SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
                        MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 3, BOOKE_PAGESZ_256K, 1),
+#endif
 #endif
 
        SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
@@ -49,7 +51,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
                        0, 4, BOOKE_PAGESZ_64K, 1),
 
        SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
-                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 5, BOOKE_PAGESZ_64K, 1),
 
        SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE,
@@ -61,7 +63,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
                        MAS3_SX|MAS3_SW|MAS3_SR, 0,
                        0, 7, BOOKE_PAGESZ_256K, 1),
 
-#ifdef CONFIG_SYS_RAMBOOT
+#if defined(CONFIG_SYS_RAMBOOT) || \
+               (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
                        CONFIG_SYS_DDR_SDRAM_BASE,
                        MAS3_SX|MAS3_SW|MAS3_SR, 0,
@@ -71,6 +74,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
                        MAS3_SX|MAS3_SW|MAS3_SR, 0,
                        0, 9, BOOKE_PAGESZ_256M, 1),
 #endif
+
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+       SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+                     0, 12, BOOKE_PAGESZ_256K, 1)
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);