serial: serial_msm: added pinmux & config

[u-boot] / board / freescale / c29xpcie / tlb.c

diff --git a/board/freescale/c29xpcie/tlb.c b/board/freescale/c29xpcie/tlb.c
index ddd1ef80b2a73f5b29c0247daeed38d9a56e595c..ef844a0b3d71efaffd10faa0e38db3243d02ea24 100644 (file)
--- a/board/freescale/c29xpcie/tlb.c
+++ b/board/freescale/c29xpcie/tlb.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -30,6 +29,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
                        MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 0, BOOKE_PAGESZ_1M, 1),
 
+#ifndef CONFIG_SPL_BUILD
        SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
                        MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
                        0, 1, BOOKE_PAGESZ_64M, 1),
@@ -42,15 +42,16 @@ struct fsl_e_tlb_entry tlb_table[] = {
        SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
                        MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 3, BOOKE_PAGESZ_256K, 1),
+#endif
 #endif
 
        SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
                        MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-                       0, 4, BOOKE_PAGESZ_4K, 1),
+                       0, 4, BOOKE_PAGESZ_64K, 1),
 
        SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
-                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-                       0, 5, BOOKE_PAGESZ_16K, 1),
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                       0, 5, BOOKE_PAGESZ_64K, 1),
 
        SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE,
                        CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS,
@@ -61,16 +62,23 @@ struct fsl_e_tlb_entry tlb_table[] = {
                        MAS3_SX|MAS3_SW|MAS3_SR, 0,
                        0, 7, BOOKE_PAGESZ_256K, 1),
 
-#ifdef CONFIG_SYS_RAMBOOT
+#if defined(CONFIG_SYS_RAMBOOT) || \
+               (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
                        CONFIG_SYS_DDR_SDRAM_BASE,
-                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
                        0, 8, BOOKE_PAGESZ_256M, 1),
        SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
                        CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
-                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
                        0, 9, BOOKE_PAGESZ_256M, 1),
 #endif
+
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+       SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+                     0, 12, BOOKE_PAGESZ_256K, 1)
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);