imx6: icorem6_rqs: Update SPL board boot order for eMMC

[u-boot] / board / freescale / common / pfuze.c

diff --git a/board/freescale/common/pfuze.c b/board/freescale/common/pfuze.c
index 2cd17944298b91b49d7b330e4b3c23af1786e0c2..69afa835623a30109014497a38b94f621df4f7de 100644 (file)
--- a/board/freescale/common/pfuze.c
+++ b/board/freescale/common/pfuze.c
@@ -5,9 +5,49 @@
  */
 
 #include <common.h>
+#include <errno.h>
 #include <power/pmic.h>
 #include <power/pfuze100_pmic.h>
 
+#ifndef CONFIG_DM_PMIC_PFUZE100
+int pfuze_mode_init(struct pmic *p, u32 mode)
+{
+       unsigned char offset, i, switch_num;
+       u32 id;
+       int ret;
+
+       pmic_reg_read(p, PFUZE100_DEVICEID, &id);
+       id = id & 0xf;
+
+       if (id == 0) {
+               switch_num = 6;
+               offset = PFUZE100_SW1CMODE;
+       } else if (id == 1) {
+               switch_num = 4;
+               offset = PFUZE100_SW2MODE;
+       } else {
+               printf("Not supported, id=%d\n", id);
+               return -EINVAL;
+       }
+
+       ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
+       if (ret < 0) {
+               printf("Set SW1AB mode error!\n");
+               return ret;
+       }
+
+       for (i = 0; i < switch_num - 1; i++) {
+               ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
+               if (ret < 0) {
+                       printf("Set switch 0x%x mode error!\n",
+                              offset + i * SWITCH_SIZE);
+                       return ret;
+               }
+       }
+
+       return ret;
+}
+
 struct pmic *pfuze_common_init(unsigned char i2cbus)
 {
        struct pmic *p;
@@ -33,10 +73,10 @@ struct pmic *pfuze_common_init(unsigned char i2cbus)
        pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
 
        /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
-       pmic_reg_read(p, PUZE_100_SW1ABCONF, &reg);
+       pmic_reg_read(p, PFUZE100_SW1ABCONF, &reg);
        reg &= ~SW1xCONF_DVSSPEED_MASK;
        reg |= SW1xCONF_DVSSPEED_4US;
-       pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
+       pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
 
        /* Set SW1C standby voltage to 0.975V */
        pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
@@ -52,3 +92,4 @@ struct pmic *pfuze_common_init(unsigned char i2cbus)
 
        return p;
 }
+#endif