Merge git://git.denx.de/u-boot-fsl-qoriq

[u-boot] / board / freescale / common / qixis.c

diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index 2b74d0201e4bdf31c090698134f50675c8c1b86d..0db0ed667002f33d6f532faf1840ad3ab4a6abac 100644 (file)
--- a/board/freescale/common/qixis.c
+++ b/board/freescale/common/qixis.c
@@ -2,13 +2,9 @@
  * Copyright 2011 Freescale Semiconductor
  * Author: Shengzhou Liu <Shengzhou.Liu@freescale.com>
  *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
+ * SPDX-License-Identifier:    GPL-2.0+
  *
  * This file provides support for the QIXIS of some Freescale reference boards.
- *
  */
 
 #include <common.h>
@@ -18,6 +14,13 @@
 #include <i2c.h>
 #include "qixis.h"
 
+#ifndef QIXIS_LBMAP_BRDCFG_REG
+/*
+ * For consistency with existing platforms
+ */
+#define QIXIS_LBMAP_BRDCFG_REG 0x00
+#endif
+
 #ifdef CONFIG_SYS_I2C_FPGA_ADDR
 u8 qixis_read_i2c(unsigned int reg)
 {
@@ -31,6 +34,7 @@ void qixis_write_i2c(unsigned int reg, u8 value)
 }
 #endif
 
+#ifdef QIXIS_BASE
 u8 qixis_read(unsigned int reg)
 {
        void *p = (void *)QIXIS_BASE;
@@ -44,6 +48,7 @@ void qixis_write(unsigned int reg, u8 value)
 
        out_8(p + reg, value);
 }
+#endif
 
 u16 qixis_read_minor(void)
 {
@@ -111,6 +116,26 @@ const char *byte_to_binary_mask(u8 val, u8 mask, char *buf)
        return buf;
 }
 
+#ifdef QIXIS_RST_FORCE_MEM
+void board_assert_mem_reset(void)
+{
+       u8 rst;
+
+       rst = QIXIS_READ(rst_frc[0]);
+       if (!(rst & QIXIS_RST_FORCE_MEM))
+               QIXIS_WRITE(rst_frc[0], rst | QIXIS_RST_FORCE_MEM);
+}
+
+void board_deassert_mem_reset(void)
+{
+       u8 rst;
+
+       rst = QIXIS_READ(rst_frc[0]);
+       if (rst & QIXIS_RST_FORCE_MEM)
+               QIXIS_WRITE(rst_frc[0], rst & ~QIXIS_RST_FORCE_MEM);
+}
+#endif
+
 void qixis_reset(void)
 {
        QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET);
@@ -122,24 +147,23 @@ void qixis_bank_reset(void)
        QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
 }
 
-/* Set the boot bank to the power-on default bank */
-void clear_altbank(void)
+static void __maybe_unused set_lbmap(int lbmap)
 {
        u8 reg;
 
-       reg = QIXIS_READ(brdcfg[0]);
-       reg = (reg & ~QIXIS_LBMAP_MASK) | QIXIS_LBMAP_DFLTBANK;
-       QIXIS_WRITE(brdcfg[0], reg);
+       reg = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
+       reg = (reg & ~QIXIS_LBMAP_MASK) | lbmap;
+       QIXIS_WRITE(brdcfg[QIXIS_LBMAP_BRDCFG_REG], reg);
 }
 
-/* Set the boot bank to the alternate bank */
-void set_altbank(void)
+static void __maybe_unused set_rcw_src(int rcw_src)
 {
        u8 reg;
 
-       reg = QIXIS_READ(brdcfg[0]);
-       reg = (reg & ~QIXIS_LBMAP_MASK) | QIXIS_LBMAP_ALTBANK;
-       QIXIS_WRITE(brdcfg[0], reg);
+       reg = QIXIS_READ(dutcfg[1]);
+       reg = (reg & ~1) | (rcw_src & 1);
+       QIXIS_WRITE(dutcfg[1], reg);
+       QIXIS_WRITE(dutcfg[0], (rcw_src >> 1) & 0xff);
 }
 
 static void qixis_dump_regs(void)
@@ -185,11 +209,55 @@ int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
        int i;
 
        if (argc <= 1) {
-               clear_altbank();
+               set_lbmap(QIXIS_LBMAP_DFLTBANK);
                qixis_reset();
        } else if (strcmp(argv[1], "altbank") == 0) {
-               set_altbank();
+               set_lbmap(QIXIS_LBMAP_ALTBANK);
                qixis_bank_reset();
+       } else if (strcmp(argv[1], "nand") == 0) {
+#ifdef QIXIS_LBMAP_NAND
+               QIXIS_WRITE(rst_ctl, 0x30);
+               QIXIS_WRITE(rcfg_ctl, 0);
+               set_lbmap(QIXIS_LBMAP_NAND);
+               set_rcw_src(QIXIS_RCW_SRC_NAND);
+               QIXIS_WRITE(rcfg_ctl, 0x20);
+               QIXIS_WRITE(rcfg_ctl, 0x21);
+#else
+               printf("Not implemented\n");
+#endif
+       } else if (strcmp(argv[1], "sd") == 0) {
+#ifdef QIXIS_LBMAP_SD
+               QIXIS_WRITE(rst_ctl, 0x30);
+               QIXIS_WRITE(rcfg_ctl, 0);
+               set_lbmap(QIXIS_LBMAP_SD);
+               set_rcw_src(QIXIS_RCW_SRC_SD);
+               QIXIS_WRITE(rcfg_ctl, 0x20);
+               QIXIS_WRITE(rcfg_ctl, 0x21);
+#else
+               printf("Not implemented\n");
+#endif
+       } else if (strcmp(argv[1], "sd_qspi") == 0) {
+#ifdef QIXIS_LBMAP_SD_QSPI
+               QIXIS_WRITE(rst_ctl, 0x30);
+               QIXIS_WRITE(rcfg_ctl, 0);
+               set_lbmap(QIXIS_LBMAP_SD_QSPI);
+               set_rcw_src(QIXIS_RCW_SRC_SD);
+               qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20);
+               qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21);
+#else
+               printf("Not implemented\n");
+#endif
+       } else if (strcmp(argv[1], "qspi") == 0) {
+#ifdef QIXIS_LBMAP_QSPI
+               QIXIS_WRITE(rst_ctl, 0x30);
+               QIXIS_WRITE(rcfg_ctl, 0);
+               set_lbmap(QIXIS_LBMAP_QSPI);
+               set_rcw_src(QIXIS_RCW_SRC_QSPI);
+               qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20);
+               qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21);
+#else
+               printf("Not implemented\n");
+#endif
        } else if (strcmp(argv[1], "watchdog") == 0) {
                static char *period[9] = {"2s", "4s", "8s", "16s", "32s",
                                          "1min", "2min", "4min", "8min"};
@@ -228,6 +296,10 @@ U_BOOT_CMD(
        "Reset the board using the FPGA sequencer",
        "- hard reset to default bank\n"
        "qixis_reset altbank - reset to alternate bank\n"
+       "qixis_reset nand - reset to nand\n"
+       "qixis_reset sd - reset to sd\n"
+       "qixis_reset sd_qspi - reset to sd with qspi support\n"
+       "qixis_reset qspi - reset to qspi\n"
        "qixis watchdog <watchdog_period> - set the watchdog period\n"
        "       period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n"
        "qixis_reset dump - display the QIXIS registers\n"