Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze

[u-boot] / board / freescale / corenet_ds / eth_hydra.c

diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c
index 962f380383a3d6744527748165fb07ed66c33998..55437e843d62c245bc34acbbe1028fbb0766376e 100644 (file)
--- a/board/freescale/corenet_ds/eth_hydra.c
+++ b/board/freescale/corenet_ds/eth_hydra.c
@@ -2,23 +2,7 @@
  * Copyright 2009-2011 Freescale Semiconductor, Inc.
  * Author: Timur Tabi <timur@freescale.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 /*
@@ -71,14 +55,14 @@
 #include <fsl_mdio.h>
 #include <malloc.h>
 #include <fdt_support.h>
-#include <asm/fsl_dtsec.h>
+#include <fsl_dtsec.h>
 
 #include "../common/ngpixis.h"
 #include "../common/fman.h"
 
 #ifdef CONFIG_FMAN_ENET
 
-#define BRDCFG1_EMI1_SEL_MASK  0x70
+#define BRDCFG1_EMI1_SEL_MASK  0x78
 #define BRDCFG1_EMI1_SEL_SLOT1 0x10
 #define BRDCFG1_EMI1_SEL_SLOT2 0x20
 #define BRDCFG1_EMI1_SEL_SLOT5 0x30
@@ -92,6 +76,8 @@
 
 #define BRDCFG2_REG_GPIO_SEL   0x20
 
+#define PHY_BASE_ADDR          0x00
+
 /*
  * BRDCFG1 mask and value for each MAC
  *
@@ -184,7 +170,7 @@ static int hydra_mdio_init(char *realbusname, char *fakebusname)
        bus->read = hydra_mdio_read;
        bus->write = hydra_mdio_write;
        bus->reset = hydra_mdio_reset;
-       sprintf(bus->name, fakebusname);
+       strcpy(bus->name, fakebusname);
 
        hmdio->realbus = miiphy_get_dev_by_name(realbusname);
 
@@ -216,6 +202,8 @@ static void fdt_set_mdio_mux(void *fdt, const char *alias, u32 mux)
        if (!path)
                path = alias;
 
+       do_fixup_by_path(fdt, path, "reg",
+                        &mux, sizeof(mux), 1);
        do_fixup_by_path(fdt, path, "fsl,hydra-mdio-muxval",
                         &mux, sizeof(mux), 1);
 }
@@ -264,11 +252,12 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
                return;
        }
 
-       if (mux == BRDCFG1_EMI1_SEL_RGMII) {
+       if (mux == (BRDCFG1_EMI1_SEL_RGMII | BRDCFG1_EMI1_EN)) {
                /* RGMII */
                /* The RGMII PHY is identified by the MAC connected to it */
                sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC4 ? 0 : 1);
                fdt_set_phy_handle(fdt, compat, addr, phy);
+               return;
        }
 
        /* If it's not RGMII or XGMII, it must be SGMII */
@@ -381,6 +370,7 @@ int board_eth_init(bd_t *bis)
        struct tgec_mdio_info tgec_mdio_info;
        unsigned int i, slot;
        int lane;
+       struct mii_dev *bus;
 
        printf("Initializing Fman\n");
 
@@ -486,6 +476,9 @@ int board_eth_init(bd_t *bis)
                }
        }
 
+       bus = miiphy_get_dev_by_name("HYDRA_SGMII_MDIO");
+       set_sgmii_phy(bus, FM1_DTSEC1, CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR);
+
        /*
         * For 10G, we only support one XAUI card per Fman.  If present, then we
         * force its routing and never touch those bits again, which removes the