#include <asm/arch/immap_ls102xa.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
-#include <asm/arch/ls102xa_stream_id.h>
#include <asm/arch/ls102xa_soc.h>
#include <asm/arch/ls102xa_devdis.h>
#include <asm/arch/ls102xa_sata.h>
#include <fsl_sec.h>
#include <spl.h>
#include <fsl_devdis.h>
-
+#include <fsl_validate.h>
+#include <fsl_ddr.h>
#include "../common/sleep.h"
#include "../common/qixis.h"
#include "ls1021aqds_qixis.h"
#ifdef CONFIG_U_QE
-#include "../../../drivers/qe/qe.h"
+#include <fsl_qe.h>
#endif
#define PIN_MUX_SEL_CAN 0x03
int checkboard(void)
{
-#ifndef CONFIG_QSPI_BOOT
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
char buf[64];
#endif
#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
#endif
-#ifndef CONFIG_QSPI_BOOT
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
QIXIS_READ(id), QIXIS_READ(arch));
* before accessing DDR SPD.
*/
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
- gd->ram_size = initdram(0);
-
- return 0;
+ return fsl_initdram();
}
#ifdef CONFIG_FSL_ESDHC
#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
- struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
+ CONFIG_SYS_CCI400_OFFSET);
unsigned int major;
#ifdef CONFIG_NAND_BOOT
#ifdef CONFIG_SCSI_AHCI_PLAT
ls1021a_sata_init();
#endif
+#ifdef CONFIG_CHAIN_OF_TRUST
+ fsl_setenv_chain_of_trust();
+#endif
return 0;
}
return 0;
}
-struct liodn_id_table sec_liodn_tbl[] = {
- SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
- SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
- SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
- SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
- SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
- SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
- SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
- SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
- SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
- SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
- SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
- SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
- SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
- SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
- SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
- SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
-};
-
-struct smmu_stream_id dev_stream_id[] = {
- { 0x100, 0x01, "ETSEC MAC1" },
- { 0x104, 0x02, "ETSEC MAC2" },
- { 0x108, 0x03, "ETSEC MAC3" },
- { 0x10c, 0x04, "PEX1" },
- { 0x110, 0x05, "PEX2" },
- { 0x114, 0x06, "qDMA" },
- { 0x118, 0x07, "SATA" },
- { 0x11c, 0x08, "USB3" },
- { 0x120, 0x09, "QE" },
- { 0x124, 0x0a, "eSDHC" },
- { 0x128, 0x0b, "eMA" },
- { 0x14c, 0x0c, "2D-ACE" },
- { 0x150, 0x0d, "USB2" },
- { 0x18c, 0x0e, "DEBUG" },
-};
-
int board_init(void)
{
- struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
+ CONFIG_SYS_CCI400_OFFSET);
unsigned int major;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
+ erratum_a010315();
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
+ erratum_a009942_check_cpo();
+#endif
major = get_soc_major_rev();
if (major == SOC_MAJOR_VER_1_0) {
/* Set CCI-400 control override register to
config_serdes_mux();
#endif
- ls1021x_config_caam_stream_id(sec_liodn_tbl,
- ARRAY_SIZE(sec_liodn_tbl));
- ls102xa_config_smmu_stream_id(dev_stream_id,
- ARRAY_SIZE(dev_stream_id));
-
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
- enable_layerscape_ns_access();
-#endif
+ ls102xa_smmu_stream_id_init();
#ifdef CONFIG_U_QE
u_qe_init();
#if defined(CONFIG_DEEP_SLEEP)
void board_sleep_prepare(void)
{
- struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
+ struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
+ CONFIG_SYS_CCI400_OFFSET);
unsigned int major;
major = get_soc_major_rev();