]> git.sur5r.net Git - u-boot/blobdiff - board/freescale/ls1043aqds/ddr.c
Merge git://git.denx.de/u-boot-fsl-qoriq
[u-boot] / board / freescale / ls1043aqds / ddr.c
index 705e3843f4f163656612da27ed5cd94dffdbb954..b22d3784dce60dd2af32898bc664eb3e98c6e00a 100644 (file)
@@ -96,6 +96,9 @@ found:
        popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
        popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
                          DDR_CDR2_VREF_OVRD(70);       /* Vref = 70% */
+
+       /* optimize cpo for erratum A-009942 */
+       popts->cpo_sample = 0x59;
 #else
        popts->cswl_override = DDR_CSWL_CS0;
 
@@ -105,27 +108,26 @@ found:
 #endif
 }
 
-phys_size_t initdram(int board_type)
+int fsl_initdram(void)
 {
        phys_size_t dram_size;
 
 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
-       return fsl_ddr_sdram_size();
+       gd->ram_size = fsl_ddr_sdram_size();
+
+       return 0;
 #else
        puts("Initializing DDR....using SPD\n");
 
        dram_size = fsl_ddr_sdram();
 #endif
+       erratum_a008850_post();
 
 #ifdef CONFIG_FSL_DEEP_SLEEP
        fsl_dp_ddr_restore();
 #endif
 
-       return dram_size;
-}
+       gd->ram_size = dram_size;
 
-void dram_init_banksize(void)
-{
-       gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-       gd->bd->bi_dram[0].size = gd->ram_size;
+       return 0;
 }