armv8: layerscape: Fix DDR size calcuation for SPL build

[u-boot] / board / freescale / ls1043aqds / eth.c

diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c
index b7fc360e2ccc649b1cbbe0fd1cbe431febf5a207..bf263761f1db76da6210af847f1363ebd75b9cce 100644 (file)
--- a/board/freescale/ls1043aqds/eth.c
+++ b/board/freescale/ls1043aqds/eth.c
@@ -7,9 +7,11 @@
 #include <common.h>
 #include <asm/io.h>
 #include <netdev.h>
+#include <fdt_support.h>
 #include <fm_eth.h>
 #include <fsl_mdio.h>
 #include <fsl_dtsec.h>
+#include <libfdt.h>
 #include <malloc.h>
 #include <asm/arch/fsl_serdes.h>
 
@@ -136,7 +138,7 @@ static int ls1043aqds_mdio_init(char *realbusname, u8 muxval)
        bus->read = ls1043aqds_mdio_read;
        bus->write = ls1043aqds_mdio_write;
        bus->reset = ls1043aqds_mdio_reset;
-       sprintf(bus->name, ls1043aqds_mdio_name_for_muxval(muxval));
+       strcpy(bus->name, ls1043aqds_mdio_name_for_muxval(muxval));
 
        pmdio->realbus = miiphy_get_dev_by_name(realbusname);
 
@@ -174,9 +176,9 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
        } else if (fm_info_get_enet_if(port) ==
                   PHY_INTERFACE_MODE_SGMII_2500) {
                /* 2.5G SGMII interface */
-               f_link.phy_id = port;
-               f_link.duplex = 1;
-               f_link.link_speed = 1000;
+               f_link.phy_id = cpu_to_fdt32(port);
+               f_link.duplex = cpu_to_fdt32(1);
+               f_link.link_speed = cpu_to_fdt32(1000);
                f_link.pause = 0;
                f_link.asym_pause = 0;
                /* no PHY for 2.5G SGMII */
@@ -239,9 +241,9 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
        } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
                   port == FM1_10GEC1) {
                /* XFI interface */
-               f_link.phy_id = port;
-               f_link.duplex = 1;
-               f_link.link_speed = 10000;
+               f_link.phy_id = cpu_to_fdt32(port);
+               f_link.duplex = cpu_to_fdt32(1);
+               f_link.link_speed = cpu_to_fdt32(10000);
                f_link.pause = 0;
                f_link.asym_pause = 0;
                /* no PHY for XFI */