serial: serial_msm: added pinmux & config

[u-boot] / board / freescale / ls1046ardb / ddr.c

diff --git a/board/freescale/ls1046ardb/ddr.c b/board/freescale/ls1046ardb/ddr.c
index a16f7bc83a91a0dcf2ae061051d6d5d059423cb4..82b1b1d9eaae29585156b81ff9696d161b8a55c1 100644 (file)
--- a/board/freescale/ls1046ardb/ddr.c
+++ b/board/freescale/ls1046ardb/ddr.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2016 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -11,6 +10,7 @@
 #ifdef CONFIG_FSL_DEEP_SLEEP
 #include <fsl_sleep.h>
 #endif
+#include <asm/arch/clock.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -28,7 +28,10 @@ void fsl_ddr_board_options(memctl_options_t *popts,
        if (!pdimm->n_ranks)
                return;
 
-       pbsp = udimms[0];
+       if (popts->registered_dimm_en)
+               pbsp = rdimms[0];
+       else
+               pbsp = udimms[0];
 
        /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
         * freqency and n_banks specified in board_specific_parameters table.
@@ -65,8 +68,6 @@ found:
              pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
 
        popts->data_bus_width = 0;      /* 64-bit data bus */
-       popts->otf_burst_chop_en = 0;
-       popts->burst_length = DDR_BL8;
        popts->bstopre = 0;             /* enable auto precharge */
 
        /*
@@ -93,7 +94,7 @@ found:
                          DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
 
        /* optimize cpo for erratum A-009942 */
-       popts->cpo_sample = 0x70;
+       popts->cpo_sample = 0x61;
 }
 
 int fsl_initdram(void)
@@ -101,7 +102,9 @@ int fsl_initdram(void)
        phys_size_t dram_size;
 
 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
-       return fsl_ddr_sdram_size();
+       gd->ram_size = fsl_ddr_sdram_size();
+
+       return 0;
 #else
        puts("Initializing DDR....using SPD\n");