SPDX: Convert all of our single license tags to Linux Kernel style

[u-boot] / board / freescale / ls1046ardb / ls1046ardb.c

diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c
index 585c807818550538165b1bba7ececb7850ddd289..feb5c2448a0c1918884ec82b9818efca40f0a4fc 100644 (file)
--- a/board/freescale/ls1046ardb/ls1046ardb.c
+++ b/board/freescale/ls1046ardb/ls1046ardb.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2016 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -19,10 +18,20 @@
 #include <fm_eth.h>
 #include <fsl_csu.h>
 #include <fsl_esdhc.h>
+#include <power/mc34vr500_pmic.h>
 #include "cpld.h"
+#include <fsl_sec.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+int board_early_init_f(void)
+{
+       fsl_lsch2_early_init_f();
+
+       return 0;
+}
+
+#ifndef CONFIG_SPL_BUILD
 int checkboard(void)
 {
        static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
@@ -55,34 +64,67 @@ int checkboard(void)
        return 0;
 }
 
-int dram_init(void)
+int board_init(void)
 {
-       gd->ram_size = initdram(0);
+       struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+#ifdef CONFIG_SECURE_BOOT
+       /*
+        * In case of Secure Boot, the IBR configures the SMMU
+        * to allow only Secure transactions.
+        * SMMU must be reset in bypass mode.
+        * Set the ClientPD bit and Clear the USFCFG Bit
+        */
+       u32 val;
+       val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+       out_le32(SMMU_SCR0, val);
+       val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+       out_le32(SMMU_NSCR0, val);
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+       sec_init();
+#endif
+
+#ifdef CONFIG_FSL_LS_PPA
+       ppa_init();
+#endif
+
+       /* invert AQR105 IRQ pins polarity */
+       out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
 
        return 0;
 }
 
-int board_early_init_f(void)
+int board_setup_core_volt(u32 vdd)
 {
-       fsl_lsch2_early_init_f();
+       bool en_0v9;
+
+       en_0v9 = (vdd == 900) ? true : false;
+       cpld_select_core_volt(en_0v9);
 
        return 0;
 }
 
-int board_init(void)
+int get_serdes_volt(void)
 {
-       struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+       return mc34vr500_get_sw_volt(SW4);
+}
 
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
-       enable_layerscape_ns_access();
-#endif
+int set_serdes_volt(int svdd)
+{
+       return mc34vr500_set_sw_volt(SW4, svdd);
+}
 
-#ifdef CONFIG_FSL_LS_PPA
-       ppa_init();
-#endif
+int power_init_board(void)
+{
+       int ret;
 
-       /* invert AQR105 IRQ pins polarity */
-       out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
+       ret = power_mc34vr500_init(0);
+       if (ret)
+               return ret;
+
+       setup_chip_volt();
 
        return 0;
 }
@@ -134,3 +176,4 @@ int ft_board_setup(void *blob, bd_t *bd)
 
        return 0;
 }
+#endif