LS2080ARDB: QSPI boot: Secure Boot image validation

[u-boot] / board / freescale / ls2080aqds / eth.c

diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c
index 8c44aacdba36228baf94626a98c660776732e7cf..aca29bc3613e8d6404b2d9b5e11efb261b25bf25 100644 (file)
--- a/board/freescale/ls2080aqds/eth.c
+++ b/board/freescale/ls2080aqds/eth.c
@@ -23,7 +23,7 @@
 
 #define MC_BOOT_ENV_VAR "mcinitcmd"
 
-#ifdef CONFIG_FSL_MC_ENET
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks.
  *   Bank 1 -> Lanes A, B, C, D, E, F, G, H
  *   Bank 2 -> Lanes A,B, C, D, E, F, G, H
@@ -449,7 +449,7 @@ static void initialize_dpmac_to_slot(void)
                >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
 
        char *env_hwconfig;
-       env_hwconfig = getenv("hwconfig");
+       env_hwconfig = env_get("hwconfig");
 
        switch (serdes1_prtcl) {
        case 0x07:
@@ -603,7 +603,7 @@ void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
                >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
 
        int *riser_phy_addr;
-       char *env_hwconfig = getenv("hwconfig");
+       char *env_hwconfig = env_get("hwconfig");
 
        if (hwconfig_f("xqsgmii", env_hwconfig))
                riser_phy_addr = &xqsgii_riser_phy_addr[0];
@@ -835,7 +835,7 @@ void ls2080a_handle_phy_interface_xsgmii(int i)
 int board_eth_init(bd_t *bis)
 {
        int error;
-#ifdef CONFIG_FSL_MC_ENET
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
        struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
        int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
                                FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
@@ -849,7 +849,7 @@ int board_eth_init(bd_t *bis)
        unsigned int i;
        char *env_hwconfig;
 
-       env_hwconfig = getenv("hwconfig");
+       env_hwconfig = env_get("hwconfig");
 
        initialize_dpmac_to_slot();