]> git.sur5r.net Git - u-boot/blobdiff - board/freescale/ls2080aqds/ls2080aqds.c
imx: mx6sllevk: add plugin support
[u-boot] / board / freescale / ls2080aqds / ls2080aqds.c
index e1a521d0805c2aac5fa8d6faa3f2b0e333bf20bf..73a61fd75aa12a3c6f7f2dfcbfca7a9b34bea5e6 100644 (file)
@@ -12,7 +12,6 @@
 #include <asm/io.h>
 #include <fdt_support.h>
 #include <libfdt.h>
-#include <fsl_debug_server.h>
 #include <fsl-mc/fsl_mc.h>
 #include <environment.h>
 #include <i2c.h>
@@ -26,6 +25,7 @@
 
 #define PIN_MUX_SEL_SDHC       0x00
 #define PIN_MUX_SEL_DSPI       0x0a
+#define SCFG_QSPICLKCTRL_DIV_20        (5 << 27)
 
 #define SET_SDHC_MUX_SEL(reg, value)   ((reg & 0xf0) | value)
 
@@ -80,6 +80,8 @@ int checkboard(void)
                puts("PromJet\n");
        else if (sw == 0x9)
                puts("NAND\n");
+       else if (sw == 0xf)
+               puts("QSPI\n");
        else if (sw == 0x15)
                printf("IFCCard\n");
        else
@@ -207,6 +209,15 @@ int board_init(void)
        else
                config_board_mux(MUX_TYPE_SDHC);
 
+#if defined(CONFIG_NAND) && defined(CONFIG_FSL_QSPI)
+       val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
+
+       if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
+               QIXIS_WRITE(brdcfg[9],
+                           (QIXIS_READ(brdcfg[9]) & 0xf8) |
+                            FSL_QIXIS_BRDCFG9_QSPI);
+#endif
+
 #ifdef CONFIG_ENV_IS_NOWHERE
        gd->env_addr = (ulong)&default_environment[0];
 #endif
@@ -218,7 +229,14 @@ int board_init(void)
 
 int board_early_init_f(void)
 {
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+       i2c_early_init_f();
+#endif
        fsl_lsch3_early_init_f();
+#ifdef CONFIG_FSL_QSPI
+       /* input clk: 1/2 platform clk, output: input/20 */
+       out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20);
+#endif
        return 0;
 }
 
@@ -228,7 +246,7 @@ void detail_board_ddr_info(void)
        print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
        print_ddr_info(0);
 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
-       if (gd->bd->bi_dram[2].size) {
+       if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
                puts("\nDP-DDR ");
                print_size(gd->bd->bi_dram[2].size, "");
                print_ddr_info(CONFIG_DP_DDR_CTRL);
@@ -246,9 +264,6 @@ int dram_init(void)
 #if defined(CONFIG_ARCH_MISC_INIT)
 int arch_misc_init(void)
 {
-#ifdef CONFIG_FSL_DEBUG_SERVER
-       debug_server_init();
-#endif
 #ifdef CONFIG_FSL_CAAM
        sec_init();
 #endif
@@ -277,12 +292,16 @@ void fdt_fixup_board_enet(void *fdt)
        else
                fdt_status_fail(fdt, offset);
 }
+
+void board_quiesce_devices(void)
+{
+       fsl_mc_ldpaa_exit(gd->bd);
+}
 #endif
 
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
-       int err;
        u64 base[CONFIG_NR_DRAM_BANKS];
        u64 size[CONFIG_NR_DRAM_BANKS];
 
@@ -296,11 +315,10 @@ int ft_board_setup(void *blob, bd_t *bd)
 
        fdt_fixup_memory_banks(blob, base, size, 2);
 
+       fsl_fdt_fixup_dr_usb(blob, bd);
+
 #ifdef CONFIG_FSL_MC_ENET
        fdt_fixup_board_enet(blob);
-       err = fsl_mc_ldpaa_exit(bd);
-       if (err)
-               return err;
 #endif
 
        return 0;