snowball: Add support for ux500 based snowball board

[u-boot] / board / freescale / m5271evb / m5271evb.c

diff --git a/board/freescale/m5271evb/m5271evb.c b/board/freescale/m5271evb/m5271evb.c
index e089d5f02f1ff7c473d90d884c4207ca99dbc49e..446f102e58c2bf42d0764a8e45c9f27d8dd4a447 100644 (file)
--- a/board/freescale/m5271evb/m5271evb.c
+++ b/board/freescale/m5271evb/m5271evb.c
@@ -47,6 +47,7 @@ phys_size_t initdram (int board_type) {
                        MCF_GPIO_SDRAM_SDWE | MCF_GPIO_SDRAM_SCAS |
                        MCF_GPIO_SDRAM_SRAS | MCF_GPIO_SDRAM_SCKE |
                        MCF_GPIO_SDRAM_SDCS_11);
+       asm(" nop");
 
        /*
         * Check to see if the SDRAM has already been initialized
@@ -55,8 +56,9 @@ phys_size_t initdram (int board_type) {
        if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) {
                /* Initialize DRAM Control Register: DCR */
                mbar_writeShort(MCF_SDRAMC_DCR,
-                               MCF_SDRAMC_DCR_RTIM(0x01)
-                               | MCF_SDRAMC_DCR_RC(0x30));
+                               MCF_SDRAMC_DCR_RTIM(2)
+                               | MCF_SDRAMC_DCR_RC(0x2E));
+               asm(" nop");
 
                /*
                 * Initialize DACR0
@@ -66,26 +68,30 @@ phys_size_t initdram (int board_type) {
                 * PS: 32bit port size
                 */
                mbar_writeLong(MCF_SDRAMC_DACR0,
-                               MCF_SDRAMC_DACRn_BA(CFG_SDRAM_BASE>>18)
+                               MCF_SDRAMC_DACRn_BA(CONFIG_SYS_SDRAM_BASE>>18)
                                | MCF_SDRAMC_DACRn_CASL(1)
                                | MCF_SDRAMC_DACRn_CBM(3)
                                | MCF_SDRAMC_DACRn_PS(0));
+               asm(" nop");
 
                /* Initialize DMR0 */
                mbar_writeLong(MCF_SDRAMC_DMR0,
                                MCF_SDRAMC_DMRn_BAM_16M
                                | MCF_SDRAMC_DMRn_V);
+               asm(" nop");
 
                /* Set IP bit in DACR */
                mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
                                | MCF_SDRAMC_DACRn_IP);
+               asm(" nop");
 
                /* Wait at least 20ns to allow banks to precharge */
                for (i = 0; i < 5; i++)
                        asm(" nop");
 
                /* Write to this block to initiate precharge */
-               *(u32 *)(CFG_SDRAM_BASE) = 0xa5a5a5a5;
+               *(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
+               asm(" nop");
 
                /* Set RE bit in DACR */
                mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
@@ -98,6 +104,7 @@ phys_size_t initdram (int board_type) {
                /* Finish the configuration by issuing the MRS */
                mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
                                | MCF_SDRAMC_DACRn_MRS);
+               asm(" nop");
 
                /*
                 * Write to the SDRAM Mode Register A0-A11 = 0x400
@@ -108,10 +115,11 @@ phys_size_t initdram (int board_type) {
                 * Burst Type = Sequential
                 * Burst Length = 1
                 */
-               *(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xa5a5a5a5;
+               *(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xa5a5a5a5;
+               asm(" nop");
        }
 
-       return CFG_SDRAM_SIZE * 1024 * 1024;
+       return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 };
 
 int testdram (void) {