board: ls1043ardb: move sec_init to board_init

[u-boot] / board / freescale / m5282evb / m5282evb.c

diff --git a/board/freescale/m5282evb/m5282evb.c b/board/freescale/m5282evb/m5282evb.c
index 31d69231a88633abc9892a0f07bdfa1bbde529d9..39f12fb4aa2db5b3812933aab4a751161eb3e124 100644 (file)
--- a/board/freescale/m5282evb/m5282evb.c
+++ b/board/freescale/m5282evb/m5282evb.c
@@ -2,23 +2,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -36,7 +20,7 @@ phys_size_t initdram (int board_type)
 {
        u32 dramsize, i, dramclk;
 
-       dramsize = CFG_SDRAM_SIZE * 0x100000;
+       dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
        for (i = 0x13; i < 0x20; i++) {
                if (dramsize == (1 << i))
                        break;
@@ -45,7 +29,7 @@ phys_size_t initdram (int board_type)
 
        if (!(MCFSDRAMC_DACR0 & MCFSDRAMC_DACR_RE))
        {
-               dramclk = gd->bus_clk / (CFG_HZ * CFG_HZ);
+               dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ);
 
                /* Initialize DRAM Control Register: DCR */
                MCFSDRAMC_DCR = (0
@@ -55,7 +39,7 @@ phys_size_t initdram (int board_type)
 
                /* Initialize DACR0 */
                MCFSDRAMC_DACR0 = (0
-                       | MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE)
+                       | MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE)
                        | MCFSDRAMC_DACR_CASL(1)
                        | MCFSDRAMC_DACR_CBM(3)
                        | MCFSDRAMC_DACR_PS_32);
@@ -77,7 +61,7 @@ phys_size_t initdram (int board_type)
                }
 
                /* Write to this block to initiate precharge */
-               *(u32 *)(CFG_SDRAM_BASE) = 0xA5A59696;
+               *(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
                asm("nop");
 
                /* Set RE (bit 15) in DACR */
@@ -94,7 +78,7 @@ phys_size_t initdram (int board_type)
                asm("nop");
 
                /* Write to the SDRAM Mode Register */
-               *(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xA5A59696;
+               *(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
        }
        return dramsize;
 }