Merge remote-tracking branch 'u-boot-imx/master'

[u-boot] / board / freescale / m5329evb / nand.c

diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c
index 82492f69db0c29aac05bfd82866a3cf43247956b..c70c98c8a14c0c99a0092674cc0194a71983ca72 100644 (file)
--- a/board/freescale/m5329evb/nand.c
+++ b/board/freescale/m5329evb/nand.c
@@ -2,7 +2,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -36,68 +36,53 @@ DECLARE_GLOBAL_DATA_PTR;
 #include <linux/mtd/mtd.h>
 
 #define SET_CLE                0x10
-#define CLR_CLE                ~SET_CLE
 #define SET_ALE                0x08
-#define CLR_ALE                ~SET_ALE
 
-static void nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
 {
        struct nand_chip *this = mtdinfo->priv;
-/*     volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; TODO: handle wp */
-       u32 nand_baseaddr = (u32) this->IO_ADDR_W;
+       volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
 
        if (ctrl & NAND_CTRL_CHANGE) {
-               if ( ctrl & NAND_CLE )
-                       nand_baseaddr |= SET_CLE;
-               else
-                       nand_baseaddr &= CLR_CLE;
-               if ( ctrl & NAND_ALE )
-                       nand_baseaddr |= SET_ALE;
+               ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+
+               IO_ADDR_W &= ~(SET_ALE | SET_CLE);
+
+               if (ctrl & NAND_NCE)
+                       *nCE &= 0xFFFB;
                else
-                       nand_baseaddr &= CLR_ALE;
+                       *nCE |= 0x0004;
+
+               if (ctrl & NAND_CLE)
+                       IO_ADDR_W |= SET_CLE;
+               if (ctrl & NAND_ALE)
+                       IO_ADDR_W |= SET_ALE;
+
+               this->IO_ADDR_W = (void *)IO_ADDR_W;
        }
-       this->IO_ADDR_W = (void __iomem *)(nand_baseaddr);
 
        if (cmd != NAND_CMD_NONE)
                writeb(cmd, this->IO_ADDR_W);
 }
 
-static void nand_write_byte(struct mtd_info *mtdinfo, u_char byte)
-{
-       struct nand_chip *this = mtdinfo->priv;
-       *((volatile u8 *)(this->IO_ADDR_W)) = byte;
-}
-
-static u8 nand_read_byte(struct mtd_info *mtdinfo)
-{
-       struct nand_chip *this = mtdinfo->priv;
-       return (u8) (*((volatile u8 *)this->IO_ADDR_R));
-}
-
-static int nand_dev_ready(struct mtd_info *mtdinfo)
-{
-       return 1;
-}
-
 int board_nand_init(struct nand_chip *nand)
 {
-       volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
-       *((volatile u16 *)CONFIG_SYS_LATCH_ADDR) |= 0x0004;
+       gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
-       /* set up pin configuration */
-       gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
-       gpio->pddr_timer |= 0x08;
-       gpio->ppd_timer |= 0x08;
-       gpio->pclrr_timer = 0;
-       gpio->podr_timer = 0;
+       /*
+        * set up pin configuration - enabled 2nd output buffer's signals
+        * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
+        * to use nCE signal
+        */
+       clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3);
+       setbits_8(&gpio->pddr_timer, 0x08);
+       setbits_8(&gpio->ppd_timer, 0x08);
+       out_8(&gpio->pclrr_timer, 0);
+       out_8(&gpio->podr_timer, 0);
 
-       nand->chip_delay = 50;
+       nand->chip_delay = 60;
        nand->ecc.mode = NAND_ECC_SOFT;
        nand->cmd_ctrl = nand_hwcontrol;
-       nand->read_byte = nand_read_byte;
-       nand->write_byte = nand_write_byte;
-       nand->dev_ready = nand_dev_ready;
 
        return 0;
 }