#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_DIU_EN | \
CLOCK_SCCR2_I2C_EN | \
CLOCK_SCCR2_MEM_EN | \
- CLOCK_SCCR2_SPDIF_EN)
+ CLOCK_SCCR2_SPDIF_EN | \
+ CLOCK_SCCR2_USB1_EN | \
+ CLOCK_SCCR2_USB2_EN)
void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip);
* write commands in order to establish the device ID.
*/
-#ifdef CONFIG_ADS5121_REV2
+#ifdef CONFIG_MPC5121ADS_REV2
out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
#else
if (in_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) {
* Elpida MDDRC and initialization settings are an alternative
* to the Default Micron ones for all but the earliest Rev 4 boards
*/
- u32 elpida_mddrc_config[4] = {
- CONFIG_SYS_MDDRC_TIME_CFG0,
- CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA,
- CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA
- CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA,
+ ddr512x_config_t elpida_mddrc_config = {
+ .ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA,
+ .ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0,
+ .ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA,
+ .ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA,
};
u32 elpida_init_sequence[] = {
if (is_micron()) {
msize = fixed_sdram(NULL, NULL, 0);
} else {
- msize = fixed_sdram(elpida_mddrc_config,
+ msize = fixed_sdram(&elpida_mddrc_config,
elpida_init_sequence,
sizeof(elpida_init_sequence)/sizeof(u32));
}
/* Verify if enabled */
tmp_val = 0;
i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
- debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
+ debug("DVI Encoder Read: 0x%02x\n", tmp_val);
tmp_val = 0x10;
i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
/* Verify if enabled */
tmp_val = 0;
i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
- debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
+ debug("DVI Encoder Read: 0x%02x\n", tmp_val);
-#ifdef CONFIG_FSL_DIU_FB
-# if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE))
- mpc5121_diu_init();
-# endif
-#endif
return 0;
}
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 spridr = in_be32(&im->sysconf.spridr);
- printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
+ printf ("Board: MPC5121ADS rev. 0x%04x (CPLD rev. 0x%02x)\n",
brd_rev, cpld_rev);
/* initialize function mux & slew rate IO inter alia on IO Pins */
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
- fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */