Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

[u-boot] / board / freescale / mpc8260ads / mpc8260ads.c

diff --git a/board/freescale/mpc8260ads/mpc8260ads.c b/board/freescale/mpc8260ads/mpc8260ads.c
index be55626104b0c68b663ad840c7f6cf36681a2ade..b8c8ce9603e4eaff75826f4f36d235e27f37bc7b 100644 (file)
--- a/board/freescale/mpc8260ads/mpc8260ads.c
+++ b/board/freescale/mpc8260ads/mpc8260ads.c
@@ -17,23 +17,7 @@
  * Vitaly Bordug <vbordug@ru.mvista.com>
  * Added support for PCI.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -243,8 +227,8 @@ void reset_phy (void)
         * Enable autonegotiation.
         */
        bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, 16, 0x610);
-       bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, PHY_BMCR,
-                       PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+       bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_BMCR,
+                       BMCR_ANENABLE | BMCR_ANRESTART);
 #else
        /*
         * Ethernet PHY is configured (by means of configuration pins)
@@ -254,13 +238,13 @@ void reset_phy (void)
         */
 
        /* Advertise all capabilities */
-       bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, PHY_ANAR, 0x01E1);
+       bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_ADVERTISE, 0x01E1);
 
        /* Do not bypass Rx/Tx (de)scrambler */
-       bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, PHY_DCR,  0x0000);
+       bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_FCSCOUNTER,  0x0000);
 
-       bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, PHY_BMCR,
-                       PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+       bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_BMCR,
+                       BMCR_ANENABLE | BMCR_ANRESTART);
 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
 #endif /* CONFIG_MII */
 }