Generic udelay() with watchdog support

[u-boot] / board / freescale / mpc8313erdb / sdram.c

diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c
index 128cd40575d381cd5eb896a7cda8fb01c02571e4..0c4fd6854d46757e9eeb96997eee2d58b2aa4257 100644 (file)
--- a/board/freescale/mpc8313erdb/sdram.c
+++ b/board/freescale/mpc8313erdb/sdram.c
@@ -35,7 +35,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifndef CFG_8313ERDB_BROKEN_PMC
+#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
 static void resume_from_sleep(void)
 {
        u32 magic = *(u32 *)0;
@@ -58,46 +58,46 @@ static void resume_from_sleep(void)
  */
 static long fixed_sdram(void)
 {
-       u32 msize = CFG_DDR_SIZE * 1024 * 1024;
+       u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
 
-#ifndef CFG_RAMBOOT
-       volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+#ifndef CONFIG_SYS_RAMBOOT
+       volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
        u32 msize_log2 = __ilog2(msize);
 
-       im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
+       im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
        im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
-       im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
+       im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
 
        /*
         * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
         * or the DDR2 controller may fail to initialize correctly.
         */
-       udelay(50000);
+       __udelay(50000);
 
        im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
-       im->ddr.cs_config[0] = CFG_DDR_CONFIG;
+       im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
 
        /* Currently we use only one CS, so disable the other bank. */
        im->ddr.cs_config[1] = 0;
 
-       im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
-       im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
-       im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
-       im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
-       im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
+       im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
+       im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+       im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+       im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+       im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
 
-#ifndef CFG_8313ERDB_BROKEN_PMC
+#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
        if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
-               im->ddr.sdram_cfg = CFG_SDRAM_CFG | SDRAM_CFG_BI;
+               im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG | SDRAM_CFG_BI;
        else
 #endif
-               im->ddr.sdram_cfg = CFG_SDRAM_CFG;
+               im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG;
 
-       im->ddr.sdram_cfg2 = CFG_SDRAM_CFG2;
-       im->ddr.sdram_mode = CFG_DDR_MODE;
-       im->ddr.sdram_mode2 = CFG_DDR_MODE_2;
+       im->ddr.sdram_cfg2 = CONFIG_SYS_SDRAM_CFG2;
+       im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+       im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE_2;
 
-       im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+       im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
        sync();
 
        /* enable DDR controller */
@@ -109,8 +109,8 @@ static long fixed_sdram(void)
 
 phys_size_t initdram(int board_type)
 {
-       volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
-       volatile lbus83xx_t *lbc = &im->lbus;
+       volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+       volatile fsl_lbus_t *lbc = &im->lbus;
        u32 msize;
 
        if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
@@ -120,11 +120,11 @@ phys_size_t initdram(int board_type)
        msize = fixed_sdram();
 
        /* Local Bus setup lbcr and mrtpr */
-       lbc->lbcr = CFG_LBC_LBCR;
-       lbc->mrtpr = CFG_LBC_MRTPR;
+       lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+       lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
        sync();
 
-#ifndef CFG_8313ERDB_BROKEN_PMC
+#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
        if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
                resume_from_sleep();
 #endif