snowball: Add support for ux500 based snowball board

[u-boot] / board / freescale / mpc8349itx / mpc8349itx.c

diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c
index 35285b4c91e906a1b07e401ad630491f1464f39b..9cc808ed7d6978d81f9a549e625c28a9338491dd 100644 (file)
--- a/board/freescale/mpc8349itx/mpc8349itx.c
+++ b/board/freescale/mpc8349itx/mpc8349itx.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -43,23 +43,27 @@
 int fixed_sdram(void)
 {
        volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-       u32 ddr_size;           /* The size of RAM, in bytes */
-       u32 ddr_size_log2 = 0;
-
-       for (ddr_size = CONFIG_SYS_DDR_SIZE * 0x100000; ddr_size > 1; ddr_size >>= 1) {
-               if (ddr_size & 1) {
-                       return -1;
-               }
-               ddr_size_log2++;
-       }
+       /* The size of RAM, in bytes */
+       u32 ddr_size = CONFIG_SYS_DDR_SIZE << 20;
+       u32 ddr_size_log2 = __ilog2(ddr_size);
 
        im->sysconf.ddrlaw[0].ar =
            LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
        im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
 
-       /* Only one CS0 for DDR */
-       im->ddr.csbnds[0].csbnds = 0x0000000f;
-       im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
+#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
+#warning Chip select bounds is only configurable in 16MB increments
+#endif
+       im->ddr.csbnds[0].csbnds =
+               ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
+               (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
+                               CSBNDS_EA_SHIFT) & CSBNDS_EA);
+       im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+
+       /* Only one CS for DDR */
+       im->ddr.cs_config[1] = 0;
+       im->ddr.cs_config[2] = 0;
+       im->ddr.cs_config[3] = 0;
 
        debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
        debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
@@ -221,15 +225,14 @@ int misc_init_f(void)
                0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
        };
        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-       volatile fsl_lbus_t *lbus = &immap->lbus;
 
-       lbus->bank[3].br = CONFIG_SYS_BR3_PRELIM;
-       lbus->bank[3].or = CONFIG_SYS_OR3_PRELIM;
+       set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
+       set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
 
        /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
           GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000
         */
-       lbus->mamr = 0x08404440;
+       immap->im_lbc.mamr = 0x08404440;
 
        upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));