eieio();
}
-static int dev_ready(void)
+static int dev_ready(int chip_nr)
{
if (in_be32(&im->qepio.ioport[4].pdat) & 0x00002000) {
debug("nand ready\n");
.upm_cmd_offset = 8,
.upm_addr_offset = 16,
.dev_ready = dev_ready,
- .wait_pattern = 1,
+ .wait_flags = FSL_UPM_WAIT_RUN_PATTERN,
.chip_delay = 50,
};
int board_nand_init(struct nand_chip *nand)
{
- fun.upm.mxmr = &im->lbus.mamr;
- fun.upm.mdr = &im->lbus.mdr;
- fun.upm.mar = &im->lbus.mar;
+ fun.upm.mxmr = &im->im_lbc.mamr;
+ fun.upm.mdr = &im->im_lbc.mdr;
+ fun.upm.mar = &im->im_lbc.mar;
upm_setup(&fun.upm);