]> git.sur5r.net Git - u-boot/blobdiff - board/freescale/mpc8536ds/mpc8536ds.c
85xx: Fix compile warning in mpc8536ds.c
[u-boot] / board / freescale / mpc8536ds / mpc8536ds.c
index f634e17650ce20c1b243197bf3636aa16f821333..f357826fd055187b6a4ac05cb50a8fc5369bb086 100644 (file)
@@ -25,6 +25,7 @@
 #include <pci.h>
 #include <asm/processor.h>
 #include <asm/mmu.h>
+#include <asm/cache.h>
 #include <asm/immap_85xx.h>
 #include <asm/immap_fsl_pci.h>
 #include <asm/fsl_ddr_sdram.h>
 #include <libfdt.h>
 #include <spd_sdram.h>
 #include <fdt_support.h>
+#include <tsec.h>
+#include <netdev.h>
 
 #include "../common/pixis.h"
+#include "../common/sgmii_riser.h"
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void ddr_enable_ecc(unsigned int dram_size);
@@ -441,7 +445,6 @@ pci_init_board(void)
 
 int board_early_init_r(void)
 {
-       unsigned int i;
        const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
        const u8 flash_esel = 1;
 
@@ -450,11 +453,9 @@ int board_early_init_r(void)
         * so that flash can be erased properly.
         */
 
-       /* Invalidate any remaining lines of the flash from caches. */
-       for (i = 0; i < 256*1024*1024; i+=32) {
-               asm volatile ("dcbi %0,%1": : "b" (flashbase), "r" (i));
-               asm volatile ("icbi %0,%1": : "b" (flashbase), "r" (i));
-       }
+       /* Flush d-cache and invalidate i-cache of any FLASH data */
+        flush_dcache();
+        invalidate_icache();
 
        /* invalidate existing TLB entry for flash + promjet */
        disable_tlb(flash_esel);
@@ -611,7 +612,6 @@ get_board_ddr_clk(ulong dummy)
 int is_sata_supported(void)
 {
        volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-       uint devdisr = gur->devdisr;
        uint sdrs2_io_sel =
                (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
        if (sdrs2_io_sel & 0x04)
@@ -620,6 +620,45 @@ int is_sata_supported(void)
        return 1;
 }
 
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_TSEC_ENET
+       struct tsec_info_struct tsec_info[2];
+       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       int num = 0;
+       uint sdrs2_io_sel =
+               (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
+
+#ifdef CONFIG_TSEC1
+       SET_STD_TSEC_INFO(tsec_info[num], 1);
+       if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) {
+               tsec_info[num].phyaddr = 0;
+               tsec_info[num].flags |= TSEC_SGMII;
+       }
+       num++;
+#endif
+#ifdef CONFIG_TSEC3
+       SET_STD_TSEC_INFO(tsec_info[num], 3);
+       if (sdrs2_io_sel == 4) {
+               tsec_info[num].phyaddr = 1;
+               tsec_info[num].flags |= TSEC_SGMII;
+       }
+       num++;
+#endif
+
+       if (!num) {
+               printf("No TSECs initialized\n");
+               return 0;
+       }
+
+       if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6))
+               fsl_sgmii_riser_init(tsec_info, num);
+
+       tsec_eth_init(bis, tsec_info, num);
+#endif
+       return pci_eth_init(bis);
+}
+
 #if defined(CONFIG_OF_BOARD_SETUP)
 void
 ft_board_setup(void *blob, bd_t *bd)