MPC8544DS: fix board Makefile for silent build (with -s)

[u-boot] / board / freescale / mpc8548cds / init.S

diff --git a/board/freescale/mpc8548cds/init.S b/board/freescale/mpc8548cds/init.S
index a83a0952c32fe3d733f37e380f4061f358537d3f..ed0fc44939de36fb5ecea22065a631cfbf12b706 100644 (file)
--- a/board/freescale/mpc8548cds/init.S
+++ b/board/freescale/mpc8548cds/init.S
@@ -41,7 +41,7 @@
  *
  * MAS0: tlbsel, esel, nv
  * MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS2: epn, x0, x1, w, i, m, g, e
  * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
  */
 
@@ -74,10 +74,10 @@ tlb1_entry:
         * This ends up at a TLB0 Index==0 entry, and must not collide
         * with other TLB0 Entries.
         */
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 #else
 #error("Update the number of table entries in tlb1_entry")
 #endif
@@ -93,33 +93,25 @@ tlb1_entry:
         * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
         * and must not collide with other TLB0 entries.
         */
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
-                       0,0,0,0,0,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, (MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
-                       0,0,0,0,0,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, (MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
-                       0,0,0,0,0,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, (MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
-                       0,0,0,0,0,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, (MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
 
        /*
@@ -127,39 +119,36 @@ tlb1_entry:
         * 0xff000000   16M     FLASH
         * Out of reset this entry is only 4K.
         */
-       .long TLB1_MAS0(1, 0, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_BOOT_BLOCK), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_BOOT_BLOCK), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+       .long FSL_BOOKE_MAS2(CFG_BOOT_BLOCK, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_BOOT_BLOCK, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 1:       1G      Non-cacheable, guarded
         * 0x80000000   1G      PCI1/PCIE  8,9,a,b
         */
-       .long TLB1_MAS0(1, 1, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 1, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
+       .long FSL_BOOKE_MAS2(CFG_PCI_PHYS, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
 #ifdef CFG_RIO_MEM_PHYS
        /*
         * TLB 2:       256M    Non-cacheable, guarded
         */
-       .long TLB1_MAS0(1, 2, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS),
-                       0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 2, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_RIO_MEM_PHYS, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_RIO_MEM_PHYS,  0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 3:       256M    Non-cacheable, guarded
         */
-       .long TLB1_MAS0(1, 3, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS + 0x10000000),
-                       0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS + 0x10000000),
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 3, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_RIO_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_RIO_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 #endif
        /*
         * TLB 5:       64M     Non-cacheable, guarded
@@ -168,28 +157,28 @@ tlb1_entry:
         * 0xe210_0000  1M      PCI2 IO
         * 0xe300_0000  1M      PCIe IO
         */
-       .long TLB1_MAS0(1, 5, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 5, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 6:       64M     Cacheable, non-guarded
         * 0xf000_0000  64M     LBC SDRAM
         */
-       .long TLB1_MAS0(1, 6, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 6, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_LBC_CACHE_BASE, 0)
+       .long FSL_BOOKE_MAS3(CFG_LBC_CACHE_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 7:       64M     Non-cacheable, guarded
         * 0xf8000000   64M     CADMUS registers, relocated L2SRAM
         */
-       .long TLB1_MAS0(1, 7, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 7, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_LBC_NONCACHE_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_LBC_NONCACHE_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
 2:
        entry_end