Merge branch 'master' of git://git.denx.de/u-boot-arm

[u-boot] / board / freescale / mpc8572ds / ddr.c

diff --git a/board/freescale/mpc8572ds/ddr.c b/board/freescale/mpc8572ds/ddr.c
index 52c7d734bfc311aeab0ec96c43998efa15b572f3..adcbd58545e78589e8e060d2e317b5b25315689e 100644 (file)
--- a/board/freescale/mpc8572ds/ddr.c
+++ b/board/freescale/mpc8572ds/ddr.c
@@ -7,33 +7,10 @@
  */
 
 #include <common.h>
-#include <i2c.h>
 
 #include <asm/fsl_ddr_sdram.h>
 #include <asm/fsl_ddr_dimm_params.h>
 
-static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
-{
-       i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
-}
-
-void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
-                     unsigned int ctrl_num)
-{
-       unsigned int i;
-       unsigned int i2c_address = 0;
-
-       for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
-               if (ctrl_num == 0 && i == 0) {
-                       i2c_address = SPD_EEPROM_ADDRESS1;
-               }
-               if (ctrl_num == 1 && i == 0) {
-                       i2c_address = SPD_EEPROM_ADDRESS2;
-               }
-               get_spd(&(ctrl_dimms_spd[i]), i2c_address);
-       }
-}
-
 typedef struct {
        u32 datarate_mhz_low;
        u32 datarate_mhz_high;
@@ -127,7 +104,6 @@ void fsl_ddr_board_options(memctl_options_t *popts,
        u32 num_params;
        u32 i;
        ulong ddr_freq;
-       int matched = 0;
 
        if (!pdimm->n_ranks)
                return;
@@ -174,14 +150,15 @@ void fsl_ddr_board_options(memctl_options_t *popts,
                        popts->cpo_override = pbsp->cpo;
                        popts->write_data_delay = pbsp->write_data_delay;
                        popts->twoT_en = pbsp->force_2T;
-                       matched = 1;
                        break;
                }
                pbsp++;
        }
 
-       if (!matched)
-               printf("Warning: board specific timing not found!\n");
+       if (i == num_params) {
+               printf("Warning: board specific timing not found "
+                       "for data rate %lu MT/s!\n", ddr_freq);
+       }
 
        /*
         * Factors to consider for half-strength driver enable: